Stratix V FPGAs: Built for Bandwidth

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Altera's 28-nm Stratix^® V FPGAs deliver the industry's highest bandwidth, highest level of system integration, and ultimate flexibility with reduced cost and the lowest total power for high-end applications.

Stratix V FPGA Advantages
- - Attain Breakthrough Bandwidth with Power-Efficient Transceivers
  - Integrated 28.05- and 14.1-Gbps transceivers, with up to 50 percent lower transceiver power compared to previous-generation devices
    
    Up to 6 x72 DDR3 memory interfaces at 1,066 MHz
    
    2.5 TMACS of signal processing performance
    
    PCI Express^® Gen3, Gen2, and Gen1 hard intellectual property (IP) support
    
    Embedded HardCopy^® Blocks and integrated hard IP in the core and transceivers, which harden critical datapath components to eliminate system bottlenecks
- - Achieve Higher Integration on a Single Chip and Reduce Your Costs
  - Double the density without a cost and power penalty, through Embedded HardCopy Blocks, which deliver up to 14.3M ASIC gates or up to 1.19M logic elements. The blocks harden standard or logic-intensive functions including interface protocols like PCI Express Gen3, Gen2, and Gen1, and application-specific functions like 40G/100G/400G.
    
    Partial reconfiguration, which enables you to reduce the size of FPGAs, saving board space, cost, and power
    
    Fractional phase-locked loops (fPLLs), which provide increased clocking flexibility and replace on-board voltage-controlled crystal oscillators (VCXOs)
    
    Integrated electronic dispersion compensation (EDC) capability in transceivers, which eliminates the need for external PHY to interface to optical modules
- - Get Ultimate Flexibility for Your Designs
  - User-friendly fine-grain partial reconfiguration, which allows you to change core functionality on the fly
    
    Dynamically reconfigurable transceivers, which let you easily support multiple protocols, data rates, and physical media attachment (PMA) settings
    
    Configuration via Protocol (CvP) using the existing PCI Express link in your application, which allows for a less complex board design
- - Lower Your System Power
  - Stratix V FPGAs reduce total power by 30 percent compared to previous-generation devices through key technologies:
    
    Programmable Power Technology which maximizes core performance while simultaneously reducing power
    
    TSMC's 28-nm high-K metal gate high-performance process optimized for lower power
    
    0.85-V/0.9-V core voltage
    
    Partial reconfiguration
    
    Embedded HardCopy Blocks and integrated core and transceiver hard IP

For higher volume production, prototype with Stratix V FPGAs and migrate your designs to low-risk, low-cost HardCopy V ASICs. You'll lower power consumption by 50 percent, and achieve higher performance.

Variant	Description
*Table 1. Stratix V Family Variants*
Stratix V GT FPGA	Optimized for applications with 28.05 Gbps transceivers requiring ultra-high bandwidth and performance, such as 40G/100G/400G applications
Stratix V GX FPGA	Optimized for high-performance, high-bandwidth applications with integrated transceivers supporting backplane, chip-to-chip, and chip-to-module operation at up to 14.1 Gbps
Stratix V GS FPGA	Optimized for high-performance, variable-precision digital signal processing (DSP) applications with integrated transceivers supporting backplane, chip-to-chip, and chip-to-module operation at up to 14.1 Gbps
Stratix V E FPGA	Optimized for ASIC prototyping with 952K logic elements on the highest performance logic fabric

Figure 1. Stratix V FPGA Architecture and Features

Figure 1. Stratix V Architecture and Features

Feature	Stratix V E FPGA	Stratix V GS FPGA	Stratix V GX FPGA	Stratix V GT FPGA
*Table 2. Comparison of Stratix V Variants*
High-performance adaptive logic modules (ALMs)	359,200	262,400	359,200	234,720
Variable-precision DSP blocks (18x18)	704	3,926	798	512
M20K memory blocks	2,640	2,567	2,660	2,560
External memory interface
Partial reconfiguration
fPLL
Design security
SEU mitigation
PCI Express Gen3, Gen2, Gen1 hard IP blocks	-	Up to 2	Up to 4	1
Embedded HardCopy Blocks and hard IP	-
Transceivers ⁽¹⁾	-	14.1 Gbps / 48	14.1 Gbps / 66	28.05 Gbps / 4 12.5 Gbps / 32

Note:

Data rate / number of transceiver channels

Stratix V FPGA Applications
Stratix V FPGAs address the design challenges for applications in a variety of industries. Expand the sections below for details about specific applications.
- - 100-Gb Optical Transport Network (OTN) Multiplexing Transponder
  - Multi-standard client interfaces enabled through easy-to-use partial reconfiguration and serial transceivers with continuous data range of 600 Mbps to 14.1 Gbps
    
    Enhanced clocking flexibility with up to 44 independent transmit clock domains
    
    Integrated electronic dispersion compensation (EDC) capability in transceivers to enable direct drive of optical modules (SFP+, SFP, QSFP, CFP)
    
    28.05-Gbps transceivers for next-generation optical interfaces
    
    Advanced fPLL replacing external voltage-controlled crystal oscillators (VCXOs)
    
    For more information, read the Enabling 100-Gbit OTN Muxponder Solutions on 28-nm FPGAs (PDF) white paper.
- - 100 Gigabit Ethernet (GbE) Line Card
  - Higher system integration through highest density and hard PCS blocks for 40 GbE, 100 GbE, and Interlaken
    
    High-bandwidth data-buffering with up to 1,600-Mbps external memory interfaces
    
    Efficient implementation of packet processing and traffic management functions
    
    Higher system performance while staying within your power and cost budget
    
    For more information, read the Addressing 100-GbE Line-Card Design Challenges on 28-nm FPGAs (PDF) white paper.
- - Crossbar and Backplane Switch Fabric
  - Highest bandwidth through 66 identical transceivers with continuous data rate from 600 Mbps to 14.1 Gbps
    
    Built-in advanced signal conditioning circuitry for direct drive of 10GBASE-KR backplanes
    
    Flexible support for various line-card interfaces with partial and dynamic reconfiguration
    
    Optimized implementation of scheduling functions through high level of integration
    
    For more information, read the Integrating 100-GbE Switching Solutions on 28-nm FPGAs (PDF) white paper.
- - Military Radar Application
  - Efficient floating-point multiplication with over 1.25 TFLOPS
    
    Higher signal processing bandwidth with up to 2.5 TMACS
    
    Automatic single event upset (SEU) detection and correction
    
    Design security with enhanced Advanced Encryption Standard (AES) algorithm and 256-bit volatile and non-volatile keys
    
    Productivity-boosting tools in Quartus^® II software, including DSP Builder Advanced Blockset and incremental compilation
    
    For more information, view Altera's Military radar and sensor solution.
- - RF Card and Channel Card
  - Reduced board space, power, and cost via fewer data channels and higher throughput per channel
    
    Lower system latency and increased system performance and reliability via greater integration
    
    Design differentiation using highest DSP- and memory-to-logic ratios
    
    Higher multiple-input multiple-output (MIMO) and bandwidth density compared to competitive offering
- - Studio Video Server
  - Best-in-class serial digital interface (SDI) solution
    
    Support for multiple CODECs through user-friendly partial reconfiguration
    
    Optimal memory design with native 10-bit support
    
    Efficient video processing with high multipliers-and memory-to-logic ratios
    
    Complete solution via CODECs and 1080p video framework IP core

Stratix V FPGAs: Built for Bandwidth

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