Nios II Processor: The World's Most Versatile Embedded Processor

About the Nios II Processor

Altera's Nios^® II processor, the world's most versatile processor, according to Gartner Research, is the most widely used soft processor in the FPGA industry. The Nios II processor delivers unprecedented flexibility for your cost-sensitive, real-time, safety-critical (DO-254), ASIC-optimized, and applications processing needs. The Nios II processor supports all Altera^® SoC and FPGA families. 

What makes the Nios II processor the world's most versatile processor?

Application	Nios II Processor Core	Vendor	Description
Altera
Power and cost sensitive	Nios II economy core	Altera	With as low as 600 logic elements, the Nios II economy processor core is ideal for microcontroller applications. The Nios II economy processor core, software tools, and device drivers are offered free of charge.
Real time	Nios II standard and fast core	Altera	Absolutely deterministic, jitter free real-time performance with unique hardware real-time features Vector Interrupt Controller Tightly Coupled Memory Custom instructions (ability to use FPGA hardware to accelerate a function) Supported by industry-leading Real-Time Operating Systems (RTOS) Nios II processor is the ideal real-time processor to use with DSP Builder-based hardware accelerators to provide deterministic, high performance real-time results
Applications processing	Nios II fast core	Altera	With a simple configuration option, the Nios II fast processor core can use a memory management unit (MMU) to run embedded Linux. Both open source and commercially supported versions of Linux for Nios II processors are available.
Altera Embedded Alliance
Safety critical	Nios II SC core	HCell	Certify your design for DO-254 compliance by using the Nios II Safety Critical procesor core along with the DO-254 compliance design services offered by HCell.

Nios II Processor Feature Set and Performance

Nios II processor comprises family of three configurable 32 bit Harvard architecture cores:

• Fast (/f core): Six stage pipeline optimized for highest performance, optional MMU, or memory protection unit (MPU)
• Economy (/e core): Optimized for smallest size, is offered at no cost
• Standard (/s core): Balanced in performance and size

Summary of Perfomance

Summary of Features Supported 

Industries Most Advanced System Integration and Debug Tools

• Quartus II software includes Qsys, the industry most advanced system integration tool for processor system design. With Qsys, designers integrate processors, peripherals, memory controller, communication controllers, and custom intellectual proeprty (IP) cores in a graphical user interface and the tool automatically generates high performance system interconnect logic.
• Quartus II software system debug capabilities provide advanced debug capabilities at every level of the design:
  • Transceiver and Memory Tool Kit for protocol and memory debugging
  • SignalTap^TM II logic analyzer for signal and logic level transactions
  • Signal Probe for IO level transactions
  • System Console for register level transactions

Free Embedded Peripheral IP Cores

• Rich portfolio of Qsys-ready embedded peripheral intellectual property (IP) cores that are provided at no cost
  • DMA Controller
  • Scatter Gather DMA Controller
  • SDR SDRAM Controller
  • CFI Flash Controller
  • EPCS Serial Flash Controller
  • JTAG UART Controller
  • UART Controller
  • SPI Controller
  • PIO Controller
  • Mutex Core
  • Mailbox Core
  • Timer Core
  • Vector Interrupt Controller Core
  • Performance Counter
  • Phase-locked loop (PLL)
  • Avalon^® Interconnect Components

Free Embedded Software Tools, Software, and Middleware

Everything you need to develop robust software applications is provided for you in the Nios II EDS. You'll feel right at home with the Eclipse-based Nios II Software Build Tools for Eclipse and a full range of software and operating system support provided by Altera and its partners.

• The Nios II EDS includes:
  • Nios II Software Build Tools for Eclipse, a fully integrated graphcial development environment
  • GNU tools (GCC compiler, GDB debugger)
  • Software examples and templates, device drivers and bare metal HAL
  • Free Nichestack TCP/IP Network Stack, Nios II Edition, commercial grade network stack
  • Evalution version of Micrium's popular MicroC/OS-II RTOS

See what's new in the latest release of Nios II EDS.

Get Started Now

Start your design today with the Nios II processor by purchasing one of the many low cost evaluation or development kits available for the Nios II processor.

• Nios II Processor Evaluation Kits
  • Low cost, easy to use. For example, Nios II Embedded Evaluation Kit and Arrow's BeMicro SDK
  • Full of design examples, tutorials, and software examples
  • Many Nios II processor community contributed design examples and software on the Altera Wiki
• Altera FPGA Development Kits
  • All new kits include pre-packaged Nios II processor design examples entitled "Board Update Portal"
  • Getting started design consist of processor, Ethernet MAC with HTML web server application
• Nios II processor Getting Started Resources: Download a design example, read product documentation, or take an instructor-led training class to get started.
  • Download Nios II processor documentation
  • Download the Nios II EDS (now included with the free Quartus^® II Web Edition software
  • Purchase a Nios II processor development or evaluation kit
  • Take a Nios II processor training course
  • Get started with a Nios II processor design example
  • Visit the Nios II processor forum in the Altera Forum and interact with other Nios II processor designers
  • Visit the Embedded Processing sections in the Altera Wiki

To ship designs featuring the Nios II processor, you will need to purchase a license for the Nios II processor.