Course DescriptionThis training will describe how you can use the JTAG interface as a simple communications channel to interact with your design. You will learn how you can leverage the Virtual JTAG megafunction in the Quartus® II software v. 6.0 in order to gain greater control of your in-system verification cycle by dynamically driving and sampling values to and from selected nodes in the FPGA fabric.
At Course CompletionYou will be able to:
- Use JTAG resources to set up a simple communications interface to your design
- Develop custom on-chip verification solutions
- Develop custom applications to use in conjunction with other tools in the Quartus II on-chip verification tool suite.
PrerequisitesWe recommend completing the following courses:
- Using the Quartus II Software: An Introduction
- Familiarity with the IEEE1149.1 (JTAG) standard (For more information about the JTAG standard for Altera devices, refer to AN39 : IEEE 1149.1 (JTAG) Boundary-Scan Testing in Altera® Devices at http://www.altera.com/literature/an/an039.pdf
- Basic familiarity with the Quartus II on-chip verification tool suite.
- Familiarity with the Quartus II software.
Applicable Training CurriculumThis course is part of the following Altera training curriculum:
- ASIC-to-FPGA Designer
- FPGA Designer
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