Documentation: External Memory Interfaces

External memory interfaces including DDR, DDR2, DDR3, QDRII/+, and RLDRAM II provide caching or data storage space in the majority of end systems featuring FPGAs. Altera offers hardened physical interface (PHY) and soft controller external memory IP to maximize performance while still allowing for flexibility to accommodate various end systems. The External Memory Interface Handbook centralizes all the information you need to create a memory interface with the latest Altera FPGA families.

Get detailed information about system performance specifications in Altera FPGAs using our External Memory Interface Spec Estimator.

External Memory Interface Handbook (23 MB)

Show All / Hide All

Volume 1: Getting Started (ver 2.0, Nov 2012, 711 KB)

Section I. Altera Memory Standard Overview and Design Flow

Chapter 1. Introduction to Altera Memory Solution (ver 2.0, Nov 2012, 251 KB)
Chapter 2. Design Flow (ver 3.0, Jun 2012, 179 KB)

Volume 2: Design Guidelines (ver 3.0, Nov 2012, 14 MB)

Section I. Design Flow Guidelines

Chapter 1. Selecting Your Memory (ver 6.0, Nov 2012, 268 KB)
Chapter 2. Selecting Your FPGA (ver 5.0, Jun 2012, 133 KB)
Chapter 3. Planning Pin and FPGA Resources (ver 6.0, Nov 2012, 900 KB)
Chapter 4. DDR2 and DDR3 SDRAM Board Design Guidelines (ver 5.0, Nov 2012, 3 MB)
Chapter 5. Dual-DIMM DDR2 and DDR3 SDRAM Board Design Guidelines (ver 4.1, Jun 2012, 1 MB)
Chapter 6. LPDDR2 SDRAM Board Design Guidelines (ver 1.0, Nov 2012, 563 KB)
Chapter 7. RLDRAM II and RLDRAM 3 Board Design Guidelines (ver 3.2, Nov 2012, 333 KB)
Chapter 8. QDR II SRAM Board Design Guidelines (ver 4.2, Nov 2012, 3 MB)
Chapter 9. Implementing and Parameterizing Memory IP (ver 6.0, Nov 2012, 796 KB)
Chapter 10. Simulating Memory IP (ver 5.1, Nov 2012, 255 KB)
Chapter 11. Analyzing Timing of Memory IP (ver 4.2, Nov 2012, 1 MB)
Chapter 12. Debugging Memory IP (ver 4.2, Nov 2012, 252 KB)

Section II. Miscellaneous Guidelines

Chapter 13. HardCopy Design Migration Guidelines (ver 2.2, Nov 2012, 294 KB)
Chapter 14. Optimizing the Controller (ver 3.1, Nov 2012, 2 MB)
Chapter 15. PHY Considerations (ver 1.2, Nov 2012, 132 KB)
Chapter 16. Power Estimation Methods for External Memory Interface Designs (ver 2.2, Nov 2012, 167 KB)

Volume 3: Reference Material (ver 3.0, Nov 2012, 8 MB)

Section I. Functional Description

Chapter 1. Functional Description - UniPHY (ver 3.1, Nov 2012, 2 MB)
Chapter 2. Functional Description - ALTMEMPHY (ver 3.3, Nov 2012, 863 KB)
Chapter 3. Functional Description - Hard Memory Interface (ver 2.1, Nov 2012, 446 KB)
Chapter 4. Functional Description - HPS Memory Controller (ver 1.0, Nov 2012, 494 KB)
Chapter 5. Functional Description - HPC II (ver 2.1, Nov 2012, 494 KB)
Chapter 6. Functional Description - QDR II and QDR II+ Controller (ver 3.3, Nov 2012, 160 KB)
Chapter 7. Functional Description - RLDRAM II Controller (ver 3.3, Nov 2012, 160 KB)
Chapter 8. Functional Description - RLDRAM 3 PHY-Only IP (ver 1.0, Nov 2012, 232 KB)
Chapter 9. Functional Description - Example Top Level Project (ver 1.3, Nov 2012, 546 KB)

Section II. UniPHY Reference

Chapter 10. Introduction to UniPHY IP (ver 2.1, Nov 2012, 173 KB)
Chapter 11. Latency for UniPHY IP (ver 2.1, Nov 2012, 129 KB)
Chapter 12. Timing Diagrams for UniPHY IP (ver 2.1, Nov 2012, 1 MB)
Chapter 13. UniPHY External Memory Interface Debug Toolkit (ver 2.2, Nov 2012, 457 KB)
Chapter 14. Upgrading from ALTMEMPHY IP (ver 2.3, Nov 2012, 140 KB)

Section III. ALTMEMPHY Reference

Chapter 15. Introduction to ALTMEMPHY IP (ver 1.2, Nov 2012, 221 KB)
Chapter 16. Latency for ALTMEMPHY IP (ver 1.2, Nov 2012, 182 KB)
Chapter 17. Timing Diagrams for ALTMEMPHY IP (ver 1.3, Nov 2012, 572 KB)
Chapter 18. ALTMEMPHY Debug Toolkit (ver 1.2, Nov 2012, 388 KB)