For a general introduction to features and design flow in the Quartus II software, see the Introduction to Quartus II Software - HTML | PDF.
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Quartus II Help
Quartus II Handbook v13.1.0 (Complete Three-Volume Set) (37 MB)
Volume 1: Design and Synthesis (ver 13.1.0, Nov 2013, 20 MB)
Section I. Design Flows
Chapter 1. Managing Quartus II Projects (ver 13.1.0, Nov 2013, 2 MB) 
- Chapter 2. Design Planning with the Quartus II Software (ver 13.1.0, Nov 2013, 235 KB)
- Chapter 3. Quartus II Incremental Compilation for Hierarchical and Team-Based Design (ver 13.1.0, Nov 2013, 749 KB)
- Chapter 4. Design Planning for Partial Reconfiguration (ver 13.1.0, Nov 2013, 604 KB)
- Chapter 5. Quartus II Design Separation Flow (ver 12.0.0, Jun 2012, 2 MB)
Section II. System Design with Qsys
- Chapter 6. Creating a System with Qsys (ver 13.1.0, Nov 2013, 2 MB)
- Chapter 7. Creating Qsys Components (ver 13.1.0, Nov 2013, 825 KB)
- Chapter 8. Qsys Interconnect (ver 13.1.0, Nov 2013, 1 MB)
- Chapter 9. Optimizing Qsys System Performance (ver 13.0.0, May 2013, 2 MB)
- Chapter 10. Component Interface Tcl Reference (ver 13.1.0, Nov 2013, 687 KB)
- Chapter 11. Qsys System Design Components (ver 13.1.0, Nov 2013, 935 KB)
Section III. Design Guidelines
- Chapter 12. Recommended HDL Coding Styles (ver 13.1.0, Nov 2013, 717 KB)
- Chapter 13. Recommended Design Practices (ver 13.1.0, Nov 2013, 774 KB)
- Chapter 14. Managing Metastability with the Quartus II Software (ver 12.0.0, Jun 2012, 267 KB)
- Chapter 15. Best Practices for Incremental Compilation Partitions and Floorplan Assignments (ver 13.1.0, Nov 2013, 148 KB)
Section IV. Synthesis
- Chapter 16. Quartus II Integrated Synthesis (ver 13.1.0, Nov 2013, 868 KB)
- Chapter 17. Synopsys Synplify Support (ver 13.1.0, Nov 2013, 552 KB)
- Chapter 18. Mentor Graphics Precision Synthesis Support (ver 12.0.0, Jun 2012, 521 KB)
- Chapter 19. Analyzing Designs with Quartus II Netlist Viewers (ver 13.1.0, Nov 2013, 2 MB)
Volume 2: Design Implementation and Optimization (ver 13.1.0, Nov 2013, 9 MB)
Section I. Scripting and Constraint Entry
- Chapter 1. Constraining Designs (ver 12.1.0, Nov 2012, 186 KB)
- Chapter 2. Command-Line Scripting (ver 13.1.0, Nov 2013, 441 KB)
- Chapter 3. Tcl Scripting (ver 12.0.0, Jun 2012, 327 KB)
Section II. I/O and PCB Tools
- Chapter 4. Managing Device I/O Pins (ver 13.1.0, Nov 2013, 1 MB)
- Chapter 5. Simultaneous Switching Noise (SSN) Analysis and Optimizations (ver 12.0.0, Jun 2012, 597 KB)
- Chapter 6. Signal Integrity Analysis with Third-Party Tools (ver 13.1.0, Nov 2013, 464 KB)
- Chapter 7. Mentor Graphics PCB Design Tools Support (ver 12.0.0, Jun 2012, 733 KB)
- Chapter 8. Cadence PCB Design Tools Support (ver 12.0.0, Jun 2012, 610 KB)
- Chapter 9. Reviewing Printed Circuit Board Schematics with the Quartus II Software (ver 12.1.0, Nov 2012, 186 KB)
Section III. Area, Timing, Power, and Compilation Time Optimization
- Chapter 10. Design Optimization Overview (ver 13.1.0, Nov 2013, 183 KB)
- Chapter 11. Reducing Compilation Time (ver 13.0.0, May 2013, 195 KB)
- Chapter 12. Timing Closure and Optimization (ver 13.1.0, Nov 2013, 2 MB)
- Chapter 13. Power Optimization (ver 13.0.0, May 2013, 837 KB)
- Chapter 14. Area Optimization (ver 13.0.0, May 2013, 374 KB)
- Chapter 15. Analyzing and Optimizing the Design Floorplan with the Chip Planner (ver 13.1.0, Nov 2013, 463 KB)
- Chapter 16. Netlist Optimizations and Physical Synthesis (ver 13.1.0, Nov 2013, 258 KB)
Section IV. Engineering Change Management
- Chapter 17. Engineering Change Management with the Chip Planner (ver 12.0.0, Jun 2012, 1 MB)
Volume 3: Verification (ver 13.1.0, Nov 2013, 8 MB)
Section I. Simulation
- Chapter 1. Simulating Altera Designs (ver 13.0.0, May 2013, 458 KB)
- Chapter 2. Mentor Graphics ModelSim and QuestaSim Support (ver 12.1.0, Nov 2012, 181 KB)
- Chapter 3. Synopsys VCS and VCS MX Support (ver 12.1.0, Nov 2012, 164 KB)
- Chapter 4. Cadence Incisive Enterprise Simulator Support (ver 13.0.0, May 2013, 165 KB)
- Chapter 5. Aldec Active-HDL and Rivera-PRO Support (ver 12.1.0, Nov 2012, 153 KB)
Section II. Timing Analysis
- Chapter 6. Timing Analysis Overview (ver 12.0.0, Jun 2012, 591 KB)
- Chapter 7. The Quartus II TimeQuest Timing Analyzer (ver 13.1.0, Nov 2013, 2 MB)
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- TimeQuest Analyzer Quick Start Tutorial
Section III. Power Estimation and Analysis
- Chapter 8. PowerPlay Power Analysis (ver 13.1.0, Nov 2013, 475 KB)
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- AN 437: Power Optimization in Stratix III FPGAs
Section IV. System Debugging Tools
- Chapter 9. System Debugging Tools Overview (ver 13.1.0, Nov 2013, 359 KB)
- Chapter 10. Analyzing and Debugging Designs with the System Console (ver 13.1.0, Nov 2013, 1 MB)
- Chapter 11. Debugging Transceiver Links (ver 13.1.0, Nov 2013, 658 KB)
- Chapter 12. Quick Design Debugging Using SignalProbe (ver 13.0.0, May 2013, 289 KB)
- Chapter 13. Design Debugging Using the SignalTap II Logic Analyzer (ver 13.1.0, Nov 2013, 1 MB)
- Chapter 14. In-System Debugging Using External Logic Analyzers (ver 12.0.0, Jun 2012, 238 KB)
- Chapter 15. In-System Modification of Memory and Constants (ver 12.0.0, Jun 2012, 159 KB)
- Chapter 16. Design Debugging Using In-System Sources and Probes (ver 12.0.0, Jun 2012, 292 KB)
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- Design Example: Dynamic PLL
Section V. Formal Verification
- Chapter 17. Cadence Encounter Conformal Support (ver 13.1.0, Nov 2013, 319 KB)
Section VI. Device Programming
- Chapter 18. Quartus II Programmer (ver 13.1.0, Nov 2013, 976 KB)
Related Documentation
Release Notes
- Quartus II Software and Device Support Release Notes Version 13.1 (ver 13.1.0, Nov 2013, 310 KB)
Getting Started
- Getting Started with Quartus II Simulation Using the ModelSim-Altera Software (ver 1.0, Jun 2011, 678 KB)
Counter Design Example (3 KB) - Introduction to Quartus II Software (PDF) (ver 1.0, May 2011, 742 KB)
Introduction to Quartus II Software (HTML) (6 KB) - Quartus II Quick Start Guide (ver 7.2, Oct 2007, 537 KB)
Installation and Licensing
- Altera Software Installation and Licensing Manual (ver 13.1.0, Nov 2013, 665 KB)
QSF Settings, SDC, and Tcl Scripting Reference Manuals
- Quartus II Scripting Reference Manual (ver 9.1.1, Jul 2013, 2 MB)
- Quartus II Settings File Reference Manual (ver 13.0.1, Jul 2013, 4 MB)
- SDC and TimeQuest API Reference Manual (ver 5.0, Dec 2009, 847 KB)
Design Guidelines and Applications
- AN 563: Design Guidelines for Arria II Devices (ver 2.0, Mar 2011, 563 KB)
- Quartus II TimeQuest Timing Analyzer Cookbook (ver 1.3, Jan 2011, 313 KB)
- AN 433: Constraining and Analyzing Source-Synchronous Interfaces (ver 2.3, Jun 2010, 2 MB)
- AN 519: Stratix IV Design Guidelines (ver 1.1, May 2009, 493 KB)
- AN 466: Cyclone III Design Guidelines (ver 2.2, Aug 2013, 872 KB)
- AN 474: Implementing Stratix III and Stratix IV Programmable I/O Delay Settings in the Quartus II Software (ver 1.3, Aug 2013, 299 KB)
- AN 370: Using the Serial FlashLoader With the Quartus II Software (ver 3.2, Oct 2012, 1 MB)
- Optimize Motor Control Designs with an Integrated FPGA Design Flow (ver 1.2, May 2012, 811 KB)
- Tips and Techniques for 28-nm Design Optimization (ver 1.0, Nov 2011, 704 KB)
- Advanced Synthesis Cookbook (ver 6.0, Jul 2011, 3 MB)
Advanced Synthesis Cookbook Design Files (4 MB) - Modeling System Signal Integrity Uncertainty Considerations (ver 1.0, Jan 2011, 624 KB)
- Understanding Metastability in FPGAs (ver 1.2, Jul 2009, 584 KB)
- AN 469: Stratix III Design Guidelines (ver 1.1, May 2008, 628 KB)
- AN 428: MAX II CPLD Design Guidelines (ver 1.1, Dec 2007, 425 KB)
- Designing With Low-Level Primitives User Guide (ver 3.0, Mar 2007, 492 KB)
- AN 411: Understanding PLL Timing for Stratix II Devices (ver 1.0, Mar 2006, 1 MB)
Design Example 1 (279 KB)
Design Example 2 (233 KB)
Benchmarking and Design Migration Techniques
- AN 307: Altera Design Flow for Xilinx Users (ver 7.0, Mar 2013, 962 KB)
an307_DesignExample.zip (4 KB) - AN 311: ASIC-to-FPGA Design Methodology and Guidelines (ver 3.1, Apr 2009, 286 KB)
- Comparing IP Integration Approaches for FPGA Implementation (ver 1.1, Feb 2008, 195 KB)
- Performing Equivalent Timing Analysis Between Altera TimeQuest and Xilinx Trace (ver 1.0, Nov 2007, 1 MB)
- FPGA Performance Benchmarking Methodology (ver 1.6, Aug 2007, 246 KB)
- AN 345: Altera Design Flow for Lattice Semiconductor Users (ver 1.1, Jan 2005, 581 KB)
- TB 84: Differences in Logic Utilization between Quartus II & Synplify Report Files (ver 1.0, Nov 2002, 107 KB)
Using Megafunctions
Arithmetic
- Integer Arithmetic Megafunctions User Guide (ver 2013.06.10, Jun 2013, 2 MB)
altaccumulate_DesignExample.zip (90 KB)
altecc_DesignExample1.zip (79 KB)
altecc_DesignExample2.zip (115 KB)
altmemmult_DesignExample.zip (186 KB)
altmult_accum_DesignExample.zip (105 KB)
altmult_add_DesignExample.zip (77 KB)
altmult_complex_DesignExample.zip (156 KB)
altsqrt_DesignExample.zip (198 KB)
parallel_adder_DesignExample.zip (97 KB) - Floating-Point Megafunctions User Guide (ver 6.0, Nov 2011, 4 MB)
Floating-Point Megafunctions Design Examples (36 MB)
Communications
- AN653: Implementing the CPRI Protocol using the Deterministic Latency Transceiver PHY IP Core (ver 2013.02.08, Feb 2013, 2 MB)
an653_Reference_Design_File (346 KB)
DSP
- Automating DSP Simulation and Implementation of Military Sensor Systems (ver 1.0, Mar 2009, 373 KB)
I/O
- LVDS SERDES Transmitter / Receiver (ALTLVDS_TX and ALTLVDS_RX) Megafunctions User Guide (ver 2013.11.08, Nov 2013, 1 MB)
altlvds_DesignExample.zip (203 KB)
altlvds_DesignExample_ex2.zip (113 KB)
altlvds_DesignExample_ex3.zip (252 KB)
altlvds_DesignExample_ex4.zip (31 KB)
altlvds_DesignExample_ex5.zip (12 KB)
altlvds_ex1_msim.zip (92 KB)
altlvds_ex2_msim.zip (58 KB)
altlvds_ex3_msim.zip (104 KB)
altlvds_ex4_msim.zip (433 KB) - ALTDQ_DQS2 Megafunction User Guide (ver 2.2, Jan 2013, 2 MB)
12.1_AV_BasicDesign.qar (44 KB)
12.1_SV_BasicDesign.qar (38 KB) - User Flash Memory (ALTUFM) Megafunction User Guide (ver 3.1, May 2012, 848 KB)
alt_ufm Archive Files (72 KB)
alt_ufm ModelSim Files (16 KB) - ALTDLL and ALTDQ_DQS Megafunctions User Guide (ver 5.0, Feb 2012, 3 MB)
ALTDLL_ALTDQ_DQS_DesignExample_ex1 (42 KB)
ALTDLL_ALTDQ_DQS_DesignExample_ex2 (796 KB)
ALTDLL_ALTDQ_DQS_ex1_msim (397 KB)
ALTDLL_ALTDQ_DQS_ex2_msim (416 KB) - Phase-Locked Loop Reconfiguration Megafunction User Guide (ALTPLL_RECONFIG) (ver 6.0, Feb 2012, 2 MB)
altpll_reconfig_DesignExample_ex1.zip (167 KB)
altpll_reconfig_DesignExample_ex2.zip (189 KB)
altpll_reconfig_DesignExample_ex3.zip (316 KB)
altpll_reconfig_ex1_msim.zip (68 KB)
altpll_reconfig_ex2_msim.zip (68 KB)
altpll_reconfig_ex3_msim.zip (432 KB) - Remote System Upgrade Megafunction User Guide (ALTREMOTE_UPDATE) (ver 2013.08.16, Aug 2013, 742 KB)
altremote_update Design Example 1 (16 KB)
altremote_update Design Example 2 (16 KB)
altremote_update ModelSim Design Example 1 (12 KB)
altremote_update ModelSim Design Example 2 (12 KB) - I/O Buffer (ALTIOBUF) Megafunction User Guide (ver 3.2, Jun 2013, 1 MB)
altiobuf_design_example_1.zip (56 KB)
altiobuf_ex1_msim.zip (91 KB) - Temperature Sensor (ALTTEMP_SENSE) Megafunction User Guide (ver 3.1, Jun 2013, 622 KB)
alttemp_sense_ex1.zip (11 KB) - Active Serial Memory Interface Megafunction User Guide (ALTASMI_PARALLEL) (ver 4.1, May 2013, 805 KB)
- Phase-Locked Loop Megafunction User Guide (ALTPLL) (ver 9.0, May 2013, 1 MB)
ddr_clk.zip (98 KB)
ddr-clk-msim.zip (6 KB)
shift_clk.zip (387 KB)
shift_clk_msim.zip (10 KB) - Double Data Rate I/O Megafunction User Guide (ALTDDIO_IN, ALTDDIO_OUT, and ALTDDIO_BIDIR) (ver 6.1, Jan 2013, 694 KB)
altddio_DesignExample_ex1.zip (112 KB)
altddio_DesignExample_ex2.zip (140 KB)
altddio_ex1_msim.zip (18 KB)
altddio_ex2_msim.zip (17 KB) - Dynamic Calibrated On-Chip Termination Megafunction User Guide (ALTOCT) (ver 3.0, Feb 2012, 632 KB)
alt_oct_msim.zip (30 KB)
altoct_DesignExample.zip (30 KB) - Clock Control Block Megafunction User Guide (ALTCLKCTRL) (ver 3.0, Feb 2012, 701 KB)
altclkctrl Design Example (104 KB)
altclkctrl Design Example ModelSim (5 KB) - External Memory PHY Interface (ALTMEMPHY) (nonAFI) Megafunction User Guide (ver 7.3, Jan 2010, 3 MB)
Interfaces
- SDI II MegaCore Function User Guide (ver 2013.06.28, Jul 2013, 968 KB)
- DDR3 SDRAM High-Performance Controller and ALTMEMPHY IP User Guide (ver 1.1, Nov 2009, 2 MB)
- DDR and DDR2 SDRAM High-Performance Controllers and ALTMEMPHY IP User Gui (ver 1.1, Nov 2009, 3 MB)
- AN653: Implementing the CPRI Protocol using the Deterministic Latency Transceiver PHY IP Core (ver 2013.02.08, Feb 2013, 2 MB)
an653_Reference_Design_File (346 KB) - ASI MegaCore Function User Guide (ver 10.1, Feb 2011, 991 KB)
- HyperTransport MegaCore Function User Guide (ver 9.1, Nov 2009, 738 KB)
- DDR and DDR2 SDRAM Controller Compiler User Guide (ver 9.0, Mar 2009, 2 MB)
JTAG-Accessible Extensions
- Partial Reconfiguration Megafunction User Guide (ver 1.0, Nov 2013, 1 MB)
- Virtual JTAG (sld_virtual_jtag) Megafunction User Guide (ver 3.0, May 2013, 1 MB)
sld_virtual_jtag - Design Example 1 (140 KB)
sld_virtual_jtag - Design Example 2 (304 KB) - AN 370: Using the Serial FlashLoader With the Quartus II Software (ver 3.2, Oct 2012, 1 MB)
Memory Compiler
- RAM-Based Shift Register (ALTSHIFT_TAPS) Megafunction User Guide (ver 2.2, May 2013, 721 KB)
DE_altshift_taps.zip (5 KB) - SCFIFO and DCFIFO Megafunctions User Guide (ver 8.2, May 2013, 496 KB)
DCFIFO Design Example (33 KB)
skew_report.tcl (3 KB) - User Flash Memory (ALTUFM) Megafunction User Guide (ver 3.1, May 2012, 848 KB)
alt_ufm Archive Files (72 KB)
alt_ufm ModelSim Files (16 KB) - RAM Initializer Megafunction User Guide (ALTMEM_INIT) (ver 1.0, May 2008, 524 KB)
DE1_internalROM.zip (8 KB)
DE2_externalROM.zip (10 KB) - Internal Memory (RAM and ROM) User Guide (ver 4.3, Nov 2013, 1 MB)
Internal_Memory_DesignExample.zip (33 KB) - Shift Register Megafunction User Guide (LPM_SHIFTREG) (ver 2013.05.06, May 2013, 691 KB)
lpm_shiftreg Design Files Archive Example 1 (84 KB)
lpm_shiftreg Design Files Example 1 (80 KB)
lpm_shiftreg Design Files Archive Example 2 (75 KB)
lpm_shiftreg Design Files Example 2 (70 KB)
lpm_shiftreg ModelSim Files Example 1 (5 KB)
lpm_shiftreg ModelSim Files Example 2 (4 KB) - First-In-First-Out Partitioner Megafunction User Guide (FIFO Partitioner) (ver 1.2, Aug 2005, 327 KB)
Storage
- Parallel Flash Loader Megafunction User Guide (ver 3.1, May 2013, 1 MB)
Design Verification and Debugging
- System-Level Debugging and Monitoring of FPGA Designs (ver 1.0, Nov 2011, 425 KB)
- TimeQuest Timing Analyzer Quick Start Tutorial (ver 1.1, Dec 2009, 230 KB)
Programming Hardware
- USB Blaster Download Cable User Guide (ver 2.5, Apr 2009, 500 KB)
- EthernetBlaster Communications Cable User Guide (ver 1.1, Jul 2008, 1 MB)
- ByteBlaster II Download Cable User Guide (ver 1.4, Jul 2008, 295 KB)
- MasterBlaster Serial/USB Communications Cable User Guide (ver 1.1, Jul 2008, 222 KB)
- ByteBlasterMV Download Cable User Guide (ver 1.0, Aug 2004, 400 KB)
Other Related Documentation
- Driving Innovative Industrial Solutions (ver 1006-1.0, May 2013, 2 MB)
- Parallel Flash Loader Megafunction User Guide (ver 3.1, May 2013, 1 MB)
- AN 433: Constraining and Analyzing Source-Synchronous Interfaces (ver 2.3, Jun 2010, 2 MB)
- Implementing FPGA Design with the OpenCL Standard (ver 3.0, Nov 2012, 956 KB)
- AN 370: Using the Serial FlashLoader With the Quartus II Software (ver 3.2, Oct 2012, 1 MB)
- FPGA Power Management and Modeling Techniques (ver 2.0, Dec 2010, 560 KB)
- Guaranteeing Silicon Performance with FPGA Timing Models (ver 1.0, Aug 2010, 386 KB)
- Video and image processing solutions for military applications (ver 2.0, Jun 2009, 278 KB)
- AN 453: HardCopy II Fitting Techniques (ver 2.0, Nov 2008, 716 KB)
- AN 549: Managing Designs with Multiple FPGAs (ver 1.0, Sep 2008, 776 KB)
- Increasing Productivity With Quartus II Incremental Compilation (ver 1.0, May 2008, 169 KB)
- AN 437: Power Optimization in Stratix III FPGAs (ver 2.0, Aug 2007, 219 KB)
Related Links
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