The IP and reference designs that match the navigation topic are listed below. If the product you seek does not fit into a subcategory, it might be listed in the main category. You can also search for IP and reference designs using the text search on the main Intellectual Property page.
Product Name
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Solution Type ![]() ![]() |
Supported Devices | SOPC Builder Ready ![]() ![]() |
Qsys Compliant ![]() ![]() |
Provider ![]() ![]() |
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4K Upscaling Video Conversion Reference Design
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- | - | Altera | |
Interlaken, 100G for 28nm devices
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- | - | Altera | |
Interlaken, 100G, 12 Lanes
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- | ![]() |
Altera | |
Interlaken, 100G, 20 Lanes
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- | ![]() |
Altera | |
Interlaken, 150G, 24 Lanes
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- | ![]() |
Altera | |
Interlaken, 40G, 8 Lanes
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- | ![]() |
Altera | |
Interlaken, 50G for 28nm devices
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- | - | Altera | |
Multi-output scaler
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Altera | |
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- | - | PLDA | ||
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- | - | PLDA | ||
RapidIO, Gen 1, x1 and x4
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Altera | |
RapidIO, Gen 2, 5G Baud, x1 and x4
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Altera | |
Serial RapidIO to PCI Bridge Reference Design
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- | - | Jennic Ltd | |
Serial RapidIO to TI 6482 DSP Reference Design
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- | Altera | |
Serial RapidIO to TI 6488 DSP Reference Design
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- | Altera | |
SerialLite II
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- | - | Altera | |
SerialLite III Streaming
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- | - | Altera | |
Transceiver Signal Integrity Development Kit, Stratix V GT Edition
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Stratix V |
- | - | Altera | |
Transceiver Signal Integrity Development Kit, Stratix V GX Edition
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Stratix V |
- | - | Altera |
The use of Altera’s Qsys and SOPC Builder components, intellectual property cores, and reference designs is governed by, and subject to, the terms and conditions of the Altera Program License Subscription Agreement, the Altera MegaCore Function License Terms and Conditions, and the Altera Hardware Reference Design License Agreement respectively.