FPGA, CPLD, and ASIC solutions from Altera
30 year anniversary logo
English Site
  • 简体中文
  • 日本語
  • Download Center
  • Documentation
  • myAltera Account
  • myAltera / Logout
Forgot my username or password
  • Devices
    • CPLDs
    • FPGAs
    • ASICs
    • SoCs
    • Processors
    • Power
    • Configuration
  • Design Tools & Services
    • Design Software
    • Intellectual Property
    • Development Kits/Cables
    • Design & Support Services
  • End Markets
    • Automotive
    • Broadcast
    • Computer & Storage
    • Consumer
    • Industrial
    • Medical
    • Military
    • Test & Measurement
    • Wireless
    • Wireline
  • Technology
    • Next-Generation Technologies
    • System Design
    • DSP
    • External Memory
    • Transceivers
    • Signal Integrity
  • Training
    • Training Courses
    • Webcasts & Videos
    • Demonstrations
    • University Program
    • Events Calendar
  • Support
    • Design & Support Resources
    • Knowledge Center
    • Devices
    • Quality & Reliability
    • Design Software
    • Intellectual Property
    • Development Kits/Cables
    • Design Examples
    • Downloads
    • Forums & Wiki
    • mySupport
  • About
    • About Us
    • Corporate Responsibility
    • Partners
    • Newsroom
    • Investor Relations
    • Working at Altera
    • Contact Us
  • Buy
    • Devices
    • Design Software
    • Development & Education Kits
    • Cables & Programming Hardware
    • Intellectual Property
    • Training Credits

FPGA and CPLD Design Flow

Home > Design Tools & Services > Design Software > FPGAs & CPLDs

Next Steps

  • Download Software
  • License Software
  • Request Software DVD
  • Get Training

Buy Now

  • Buy Software
  • Purchase Development Kits
  • Buy Cables

Support

  • Get Software Support
  • View Knowledge Base
  • Use Troubleshooter
  • Join the Altera Forum

Documentation

  • Get Documentation
  • Get Handbook (PDF)
  • Get Email Updates
  • Get Product Catalog (PDF)

Compile Your First FPGA or CPLD Design Using Quartus II Software

View FPGA Video

Learn how to compile your first FPGA or CPLD design
in less than five minutes.

View Video Training Support Quick Start Guide (PDF)

Understanding Altera's FPGA and CPLD Design Flow

FPGA Design Flow CPLD Design Flow

Should I use Quartus II Web Edition software, Quartus II Subscription Edition software, or buy a development kit?

Altera offers both free Quartus® II Web Edition software and Quartus II Subscription Edition software. To help you choose, view a detailed comparison document (PDF). You can also purchase a development kit which includes reference designs, intellectual property (IP) cores, and a one-year, time-limited evaluation license for Quartus II software.

What Quartus II software documentation and learning resources are available?

Table 1 lists some of the available software documentation and learning resources.

Table 1. Documentation and Resources

Skill Level

Resource

Beginner

Online demonstrations

Beginner

Quick Start Guide for Quartus II Software (PDF)

Beginner

Tutorials (included in software)

Beginner to Intermediate

Introduction to Quartus II Software (PDF)

Intermediate to Advance

Quartus II Handbook (PDF)

All

Altera Training—Free online and instructor-led trainings

All

Webcasts

All

General Quartus II software documentation

FPGA Design Flow

The Quartus II software now features unique advantages in FPGA design flow methodology, system design, timing-closure methodology, in-system verification technology, and third-party EDA support. Highlights of Quartus II software FPGA design flow features are provided below. Figure 1 shows a high-level example of some of the Quartus II software FPGA design flow options. Some steps can be performed in a different order  from the order shown in Figure 1.

Figure 1. FPGA Design Flow

Design Entry and Synthesis Technology

Quartus II design software delivers the highest FPGA, CPLD, and HardCopy® ASIC productivity and performance and offers numerous design features to accelerate the design process:

  • Various methods of design entry
  • Scripting support
  • Incremental compilation: initial setup
  • Qsys and SOPC Builder for system-level design
  • MegaWizardTM Plug-In Manager to quickly and easily integrate a broad portfolio of IP cores
  • I/O pin assignment analysis to manage I/O pin usage early
  • Quartus II integrated synthesis
  • Third-party design entry and synthesis
  • Basic compilation flow

More Info

Verification and Board-Level Solution

Quartus II software provides the most advanced CPLD, FPGA, and HardCopy ASIC verification support available. In addition to integrating with all of the leading third-party verification tools and methodologies, Quartus II software provides:

  • TimeQuest timing analyzer
  • Integrated power analysis with the PowerPlay power analysis and optimization technology
  • Chip Planner (floorplan and chip editor)
  • SignalTap® II embedded logic analyzer (supported by the incremental compilation feature to accelerate verification cycles)
  • Register transfer level (RTL) viewer and technology map viewer
  • Third-party verification support

More Info

Optimization Tools

Quartus II design software delivers the highest productivity and performance for FPGAs, CPLDs, and HardCopy ASICs and offers numerous optimization features to enhance the design process:

  • Incremental compilation: optimization
  • Physical synthesis optimization to tune designs for peak performance
  • Design Space Explorer (DSE) automatic design optimization script
  • Timing Optimization Advisor
  • Resource Optimization Advisor

More Info

CPLD Design Flow

Easiest-to-Use CPLD Design Software

Altera’s Quartus II Subscription Edition software and the no-cost Quartus II Web Edition software support MAX® II CPLD designs with an easy-to-use and comprehensive design environment that can take CPLD design projects from start to finish (see Figure 2). Quartus II Subscription Edition and Web Edition softwares also integrate seamlessly with all leading third-party synthesis and simulation tools.

Figure 2. Quartus II Software CPLD Design Flow

Quartus II Advantages for MAX+PLUS II Users

The Quartus II software is the highest performance and easiest-to-use software available for CPLD designs. With a built-in MAX+PLUS® II look-and-feel option, MAX+PLUS II software users can get the full benefits of the advanced features and performance of Quartus II software without having to learn a new interface. See the Make the Easy Switch from MAX+PLUS II to Quartus II Software page.

Rate This Page


  • Logic Design
    • About Quartus II Software
    • Quartus II Subscription Edition
      • System Integration (Qsys)
        • System Console
      • Design Entry & Synthesis
      • Verification & Board Level
      • Optimization
    • Quartus II Web Edition
    • ModelSim-Altera
    • OpenCL
    • What's New
  • DSP Design
    • DSP Builder
  • Getting Started
    • FPGAs & CPLDs
    • HardCopy ASIC
  • Switching to Quartus II
    • ASIC Users
    • Xilinx ISE Users
    • MAX+PLUS II Users
  • Partners
    • EDA Partners
    • OpenCL Board Partners
    • OpenCL Application Developers
  • Ordering & Downloading
    • Ordering
    • Downloading
    • Licensing
Please give us feedback
Devices | Design Tools & Services | End Markets | Technology | Training | Support | About | Buy
Jobs | Investor Relations | Contact Us | Site Map | Privacy | Legal Notice
Copyright © 1995-2012 Altera Corporation. All Rights Reserved.
Altera Forum
Altera
Forum
Altera Wiki
Altera
Wiki
Email Updates
Email
Updates
Follow Us
Follow
Us