Combining the Open Computing Language (OpenCL™) programming model with Altera’s massively parallel FPGA architecture provides a powerful solution for system acceleration. The Altera® SDK for OpenCL* provides a design environment for you to easily implement OpenCL applications on FPGAs.
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Benefits of OpenCL on FPGAs
Performance
As a software programmer or system architect, how can you benefit from using OpenCL with an FPGA accelerated system?
As the "power wall" continues to prevent higher frequencies to be achieved in processors, multicore processors have become the norm. This has opened the door for parallel processing techniques and thus FPGAs, which are inherently parallel, to start playing a bigger role in the high-performance computing (HPC) world.
The approaches to finding parallelism vary for different software programmers. You can take the divide and conquer method for task parallelism, where you decompose the problem into sub problems and run them on the appropriate resources. Or, you can take the scatter-gather approach for data parallelism, sending input data to the appropriate parallel resources, and combining the results later. What FPGAs offer is pipeline parallelism, where multiple different tasks can be spawned in a push-pull configuration, with each task using different data that is supplied from the previous task with or without host interaction.
Using OpenCL, you continue to develop your code in the familiar C programming language, but target certain functions as OpenCL kernels using the additional OpenCL constructs. Then, these kernels can be sent to the available system resources, such as an FPGA, without having to learn the low-level Hardware Description Language (HDL) coding practices of FPGA designers.
In summary:
- HDL coding is the equivalent to coding in assembly language, whereas OpenCL keeps you at a higher level.
- Profile your code and determine the performance-intensive inner loop functions that make sense to hardware-accelerate as kernels in an FPGA.
- It is about performance per watt. You’re balancing high performance with a power-efficient solution in an FPGA.
- With the FPGA's fine-grain parallelism architecture, the Altera SDK for OpenCL generates only the logic you need to deliver 1/5 of the power of other hardware alternatives.
- Kernels can target FPGAs, CPUs, GPUs, and DSPs seamlessly to produce a truly heterogeneous system.
- OpenCL kernels allow for portable code that can be targeted for different families and generations of FPGAs from one project to the next, extending the life of your code.
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Design for Higher Performance and Lower Power with OpenCL on Altera FPGAs (for Software Developers)Watch this webcast to understand:
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Cost
As an embedded programmer, how can you benefit from using OpenCL with an FPGA accelerated system?
Altera SoCs combine the host and FPGA accelerator in a single package providing a low cost, real time performance acceleration solution. The SoC solution offers a significantly lower system cost and reduced power consumption over the typical CPU host, while providing an FPGA fabric to offload functions in soft logic that are impacting your real time performance. The Altera SDK for OpenCL abstracts away the typical RTL development flow for the FPGA accelerator and allows the embedded programmer to continue working in the software environment they’re comfortable with. Being a C based language, OpenCL should be very familiar with enhancements allowing for optimizations to extracting parallelism from the code effectively.
In Summary:
- Accelerate functions as OpenCL kernels in the FPGA using the Altera SDK for OpenCL.
- Abstract away the typical FPGA development flow.
- Generate an FPGA implementation of the OpenCL kernel code in a single step.
- Obsolescence-proof your designs; retarget OpenCL code to current and future SoCs without modification.
- Lower system complexity with the host and accelerator in a single package.
- Reduces system cost and power requirements.
For more information on Altera SoC products, visit the SoC page here on altera.com. See the raytracing demo running on our Cyclone V SoC development board.
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Accelerate Performance and Design Productivity with OpenCL on Altera FPGAsWatch this webcast to understand:
Watch Webcast
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What Is OpenCL?
The OpenCL standard is the first open, royalty-free, unified programming model for accelerating algorithms on heterogeneous systems. OpenCL allows the use of a C-based programming language for developing code across different platforms such as CPUs, GPUs, digital signal processors (DSP), and FPGAs.
OpenCL is a programming model for software engineers and a methodology for system architects. It is based on standard ANSI C (C99) with extensions to create parallelism. OpenCL also includes API for the host to communicate with the hardware accelerator, in hosted systems, or one kernel to communicate with another, in non-hosted systems. A key benefit of OpenCL is that it is a portable open, royalty-free standard, which is a key differentiator versus proprietary programming models.
In the OpenCL model, the user schedules tasks to command queues, of which there is at least one for each device. The OpenCL run-time then breaks the data-parallel tasks into chunks and sends them to the processing elements in the device. This is the method for a host to communicate with any hardware accelerator. It is up to the individual hardware accelerator vendors to abstract away the vendor-specific implementation. The Altera SDK for OpenCL v13.1 does this and conforms to the OpenCL 1.0 standard. For more information on the OpenCL 1.0 standard, refer to The OpenCL Specification (PDF) by Khronos.
OpenCL is supported by many vendors who are part of the Khronos group. For more information, visit http://www.khronos.org/opencl/
For an overview on OpenCL for Altera FPGAs, view the Accelerate Performance and Design Productivity with OpenCL on Altera FPGAs webcast.
What Is the Altera SDK for OpenCL?
The Altera SDK for OpenCL allows the easy implementation of applications onto FPGAs by abstracting away the complexities of FPGA design, allowing software programmers to write hardware-accelerated kernel functions in OpenCL C, an ANSI C-based language with additional OpenCL constructs.
A typical OpenCL application consists of a host program and OpenCL kernel functions. The host program is standard software written in C in which any standard C compiler, such as Microsoft Visual studio or GCC, can compile. The kernel functions are written in OpenCL C. The Altera SDK for OpenCL provides a compiler to compile these kernel functions into an FPGA image that can be run on a single or multiple FPGAs, on a single or multiple boards, to meet your real-time performance requirements.
The Altera SDK for OpenCL is a full production release, making Altera the first FPGA company to have a solution that conforms to the OpenCL specification. The Altera SDK for OpenCL is able to host the embedded ARM Cortex-A9 processor cores in SoCs, or simply stream data into the FPGA for processing. The Altera SDK for OpenCL is able to support kernels that span across multiple FPGAs and multiple boards. It also supports different memory architectures for either random memory accesses to QDR SRAM or sequential accesses to DDR SDRAM.
The Altera SDK for OpenCL supports a variety of boards. For more information about our preferred board partners and OpenCL certified boards, please visit the Altera’s Preferred Board Partner Program for OpenCL page.
How Do I Get Started?
Get started now! Altera is working with several board partners to roll out support for the Altera SDK for OpenCL. For more information or to buy a board from one of our preferred OpenCL board partners, visit the Altera’s Preferred Board Partner Program for OpenCL page. The Altera SDK for OpenCL is included with OpenCL boards from Altera’s preferred partners, but you can also create the FPGA for your own custom board.
- Buy a board from one of our preferred partners
- Download the Altera SDK for OpenCL
- Take an OpenCL training
- Register for updates on Altera’s OpenCL solution for FPGAs
Additional Resources
White Papers
- Implementing FPGA Design with the OpenCL Standard (PDF)
- Fractal Video Compression in OpenCL: An Evaluation of CPUs, GPUs, and FPGAs as Acceleration Platforms (PDF)
- Using OpenCL to Evaluate the Efficiency of CPUs, GPUs, and FPGAs for Information Filtering (PDF)
- 40Gbit AES Encryption Using OpenCL and FPGAs (PDF)
Demonstrations
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Achieve Power Efficiency in a Single Chip Solution Using OpenCL on Our SoCs |
Unified Heterogeneous Programmability of OpenCL Watch how OpenCL provides a unified platform for heterogeneous computing. In this demo, we retarget NVIDIA code written for a GPU to a Stratix® V FPGA. |
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Accelerating Algorithm Performance with OpenCL by Offloading to an FPGA Watch how OpenCL accelerates the performance of the Mandelbrot algorithm ̶ an iterative, arithmetically intensive floating-point algorithm. |
Want more? Head to the OpenCL Design Examples page to get started.
Webcast
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An Introduction to OpenCL for Altera FPGAs, 25 minutes Watch this webcast to understand:
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Training
| Instructor-led training |
Parallel Computing with OpenCL Workshop (1 day) Get an overview of parallel computing, the OpenCL standard and the OpenCL for FPGA design flow. The focus on the class is not on writing kernels, but rather going over the FPGA specific portion of creating an OpenCL environment for hardware acceleration. The workshop includes hands-on exercises and is taught by Altera application engineers who are dedicated trainers. Optimizing OpenCL for Altera FPGAs (1 day) This class focuses on writing kernel functions that are optimized for Altera FPGAs. The workshop includes hands-on exercises and is taught by Altera application engineers who are dedicated trainers. OpenCL for Altera FPGAs Training (4 days) by Acceleware  Learn how to write and optimize OpenCL applications for Altera FPGAs. You will also learn how to achieve high performance by taking advantage of the heterogeneous nature of OpenCL and the massively parallel capabilities of Altera FPGAs. The training includes innovative hands-on exercises and a series of progressive lectures. Small class sizes maximize learning and ensure a personal educational experience. |
| Free online classes |
Introduction to Parallel Computing with OpenCL (30 minutes) Writing OpenCL Programs for Altera FPGAs (1 hour) Running OpenCL on Altera FPGAs (30 minutes) |
For additional information on OpenCL, refer to the following:
- Article: OpenCL for FPGA - Bringing FPGAs to the (relative) masses Part 1
- The OpenCL Specification Version 1.0 (PDF)
- Altera SDK for OpenCL documentation
- OpenCL Design Examples
- OpenCL Application Developers
- Join the Altera Forum for OpenCL
OpenCL and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos.
* Product is based on a published Khronos Specification, and has passed the Khronos Conformance Testing Process. Current conformance status can be found at www.khronos.org/conformance.
