DSP Builder technology allows you to go from system definition and simulation using the industry-standard MathWorks Simulink tools to system implementation in a matter of minutes.
The DSP Builder Signal Compiler block reads Simulink Model Files (.mdl) that are built using DSP Builder and MegaCore® blocks and generates VHDL files and Tcl scripts for synthesis, hardware implementation, and simulation.
Figure 1 shows the DSP design implementation flow using DSP Builder.
Figure 1. DSP Builder Design Flow
Altera and Mathworks work in close collaboration to ensure that you get the price and performance benefits of Altera® FPGAs while leveraging Simulink, the industry-leading tool for model-based design from MathWorks.
Altera's Simulink-to-FPGA synthesis technology is unique in the industry in that it now supports timing-driven synthesis of a Simulink design representation.
This technology allows you for the first time to automatically generate timing-optimized register transfer level (RTL) code based on high-level Simulink design descriptions. With this new DSP Builder feature, you can achieve high-performance design implementations, running at near-peak FPGA performance, in a matter of minutes. This is a significant productivity savings compared to the hours, if not days, required to hand-optimize HDL code. For more information, view advanced blockset DSP Builder libraries.
A full overview of DSP intellectual property (IP) that works in conjunction with DSP Builder and the IP evaluation flow is available on the Altera IP MegaStoreTM website.
What People Are Saying About Altera DSP
“DSP Builder’s second-generation model-based synthesis technology allows customers to use Simulink as the modeling, simulation, and implementation environment of choice for high-performance DSP designs. This technology allows designers to vastly improve their productivity as they implement DSP functionality on Altera’s FPGAs.”
Marketing Director, Digital Signal Processing and Communications
Development Kits Supported by DSP Builder
|Product Name (Altera)||Featured Device|
|Arria II GX FPGA Development Kit||Arria II GX||EP2AGX125EF35I3|
|Arria II GX FPGA Development Kit, 6G Edition||Arria II GX||EP2AGX260FF35I3|
|Cyclone II Starter Development Kit||Cyclone II||EP2C20F484C7|
|Cyclone III LS FPGA Development Kit||Cyclone III LS||EP3CLS200F780C7|
|Cyclone IV GX FPGA Development Kit||Cyclone IV GX||EP4CGX150DF31C7|
|Cyclone IV GX Transceiver Starter Kit||Cyclone IV GX||EP4CGX15BF14C8|
|100G Development Kit, Stratix IV GT Edition||Stratix IV||EP4S100G5F45I1|
|Stratix IV E FPGA Development Kit||Stratix IV||EP4SE530H35C2|
|Stratix IV GX FPGA Development Kit, 530 Edition||Stratix IV||EP4SGX530KH40C2|
|Transceiver Signal Integrity Development Kit, Stratix IV GT Edition||Stratix IV||EP4S100G2F40I1|
|Product Name (Terasic)||Featured Device|
|DE0 Development Board||Cyclone III||EP3C16F484C6|
|DE1 Development Board||Cyclone II||EP2C20F484C7|
|DE3-150 Stratix III High Speed Rapid Prototyping System||Stratix III||EP3SL150F1152C2|
|DE3-260 Stratix III High Speed Rapid Prototyping System||Stratix III||EP3SE260F1152C2|
|DE3-340 Stratix III High Speed Rapid Prototyping System||Stratix III||EP3SL340F1152C2|
Digital Signal Processing Documents
- DSP Builder Handbook Volume 1: Introduction to DSP Builder (PDF)
- DSP Builder Release Notes and Errata (PDF)
Related Digital Signal Processing Links
- Download DSP Builder
- DSP Builder Version History and Software Requirements
- The MathWorks: MATLAB and Simulink Product Evaluation for Use with Altera DSP Builder
- DSP Builder Design Examples
- Documentation: DSP