Software support for Arria 10 FPGAs and SoCs is available as a separate download. Learn more or download now.
Quartus II Software - The Productivity and Performance Leader
Altera’s Quartus® II software is the industry's number one software in productivity and performance for CPLD, FPGA, and SoC designs.
Quartus II software v13.1 enables you to achieve unprecedented levels of design productivity by enabling more design iterations within a day, and providing the tools to capture your design intent in the most efficient way possible.
With Quartus II software v13.1, you will experience an average of 30% reduction in compile time and an additional average of 50 percent reduction for small design changes, enabling quicker design turns and faster time to market. In addition, Quartus II software v13.1 provides new capabilities, enhancements, and performance improvements to our suite of higher level design tools (i.e. Qsys, OpenCLTM, and DSP Builder) to efficiently capture your design intent, providing IP-based, C-based, or model-based entry.
Delivering the Industry's Fastest Compile Times
With Quartus II software v13.1, you can achieve an average of 30% and up to 70% percent reduction in compile times compared with the previous version without compromising fMAX performance. In addition, when making small, non-timing critical changes on large Stratix® V FPGA designs, the newly available Rapid Recompile feature can further achieve 50 percent reduction in compile times compared to a full compilation.
Altera continues to focus and commit in delivering the industry’s fastest compile times. Quartus II software v13.1 makes significant improvements on algorithm optimization and parallelization on the algorithm, and scale even better with the number of cores on your multiprocessor machine.
Figure 1 illustrates the benchmark results on high-end devices in the Quartus II software since 2011.
Figure 1: Relative Compile Times for High-End FPGAs Normalized to 2011
Improving algorithm optimization and parallelization enables the Quartus II software to maintain its leadership in compilation time.
Figure 2 shows the Quartus II software v13.1 compile time comparison with the nearest competitor.
Figure 2: Compile Time Comparison in Quartus II v13.1 vs. Competing Design Tools
Rapid Recompile is a push-button feature that allows you to reuse previous compilation results to reduce compilation time without requiring up-front design partitioning. Rapid Recompile can also reduce timing variation between successive compilation by automatically preserving the original placement and routing of portions of the design that have not been modified between compilations.
Figure 3 shows the results of using Rapid Recompile to make several small design changes to a very large Optical Transport Network (OTN) design targeting the Stratix V FPGA device. In this design, Rapid Recompile is able to implement each design change with very little disruption to the design’s overall final fMAX result.
Figure 3: Rapid Recompile Enables Faster Design Cycle while Preserving Performance
System Integration Tool that Meets Your Performance Needs
You can save significant time and effort throughout your FPGA design cycle with the Qsys system integration tool. Qsys can automatically generate the interconnects for the intellectual property (IP) functions and subsystems in your design for you. The Qsys interconnect uses a network on a chip (NoC) architecture that enables high interconnect performance, and supports different standard interfaces, including Avalon®, ARM® AMBA® AXITM, AMBA APBTM, and AMBA AHBTM interfaces. On average, the Qsys interconnect performance is 20 percent faster compared to the other competing IP integration tools. In Quartus II software v13.1, Qsys further improves your productivity with improved system visualization, allowing multiple simultaneous views of your Qsys system. This makes modifying your system, either by adding components to your system or connecting components to new peripheral, much easier.
With NoC implementations, Qsys can automatically insert pipeline stages to improve performance and close timing for your system quickly. In addition, you have the direct control to insert the pipeline stages at the critical paths on your Qsys system to help close timing.
Figure 4 shows the frequency results of the Qsys interconnect with the competing interconnect across various combinations of multiple-master-to-multiple-slave systems. On average, the Qsys interconnect performance is 20 percent faster than the competing interconnect.
Figure 4: Qsys NoC Frequency Compared to the Competing Interconnect
To learn more about the benefits of NoC architecture, read the following white paper:
- Applying the Benefits of Network on a Chip Architecture to FPGA System Design (PDF)
AMBA AXI and Altera Avalon Interoperation Using Qsys
See how you can use Qsys to integrate IP components with AMBA AXI and Altera Avalon interfaces seamlessly.Watch Demo
- Several feature enhancements for Qsys include:
- Qsys system visualization with a customizable view of your Qsys system, making it easy to modify your Qsys system
- New reset sequencer, enabling you to have direct control of logic reset bring up
- Qsys system hierarchical interconnect support that provides better component visibility in the Quartus II software, making design simulation and system debug easier
- Custom insertion of pipeline stages, enabling faster timing closure
- Expanded Transceiver Toolkit capabilities for supporting Arria® V SoCs
- Faster, scalable netlist viewer, enabling you to more efficiently and quickly catch design errors at the early stages of the design process
- Added Windows 8 64-bit platform support
Combining the Open Computing Language (OpenCL) standard, an open royalty-free parallel programming model, with the parallel performance capability of Altera FPGAs provides a powerful system acceleration solution. The Altera® SDK for OpenCL* allows an easy implementation of applications on FPGAs by abstracting away the complexities of FPGA design, allowing software programmers to write hardware-accelerated kernel functions in OpenCL C, an ANSI C-based language with additional OpenCL constructs.
The Altera SDK for OpenCL is in full production. Altera is leading the way in OpenCL integration into FPGAs by being the only FPGA company to have a solution that has passed conformance testing. You can be assured of the robustness of our OpenCL solution, as the Altera SDK for OpenCL conforms to the OpenCL specification defined by the Khronos Group.
Many customers are actively developing with the Altera SDK for OpenCL on commercial off-the-shelf (COTS) boards from our Altera Preferred Board Partner Program. We are also developing additional capabilities with customers in an early access program to allow them to develop their own custom boards to be used with our SDK for OpenCL.
To discover the high-performance, power-efficient acceleration that OpenCL provides with FPGAs:
- Visit the OpenCL for Altera FPGAs page
- Download the Altera SDK for OpenCL
- Buy a board (License included for the Altera SDK for OpenCL)
Altera SDK for OpenCL v13.1 delivers the following enhancements:
- Conformation to the OpenCL specification
- Loop pipelining and task support that allow further parallelism extraction from your code by optimizing loops and allowing resource and performance trade-offs
- Added board support through our Altera Preferred Board Partner Program
- A number of powerful beta features delivering new capabilities include:
- Using the embedded ARM Cortex™-A9 processor cores as a host within the SoC device. This provides a low-cost single-chip solution for embedded systems seeking hardware acceleration
- Fine-tuning the memory performance in your kernels by targeting different memory architectures for either random memory access to QDR SRAM or sequential access to DDR SDRAM
- Using multiple FPGAs on a single board and multiple boards to allow for rapid scaling of the system.
OpenCLTM and the OpenCL logo are trademarks of Apple Inc. used by permission by Khronos.
* Product is based on a published Khronos Specification, and has passed the Khronos Conformance Testing Process. Current conformance status can be found at www.khronos.org/conformance.
OpenCL on Altera SoCs
Discover how Altera reduces system complexity by combining both the host and accelerator in a single package, and accelerates the raytracing algorithm using OpenCL with the embedded ARM processors in our Cyclone® V SoC.
New Training Class: Optimizing OpenCL for Altera FPGAs
This course covers the optimization techniques needed to implement a high-performance OpenCL solution on an FPGA using the Altera SDK for OpenCL.
Altera’s DSP Builder, along with MathWorks’ MATLAB Simulink tools, allows you to go from system definition and simulation of digital signal processing (DSP) datapaths to hardware implementation in a matter of minutes. DSP Builder works within Simulink to automatically generate VHDL files and Tcl scripts for FPGA synthesis, hardware implementation, and simulation.
The new features in DSP Builder v13.1 include the following:
- Improved floating-point compiler
- Increased efficiency for fast Fourier transforms (FFTs) of variable sizes
- Improved folding, or time-division multiplexing, for large folding factors
- Co-design capability with MathWorks’ HDL Coder
To learn more about DSP Builder, visit the DSP Builder page.
System Console Integration with MATLAB and Simulink for Hardware in the Loop
See how System Console can be used to test algorithms running live in hardware via Simulink.Watch Demo
To learn more:
- Visit the Altera’s System in the Loop page
Download the new white paper discussing the Hardware in the Loop methodology
|Arria V FPGAs||
|Cyclone V FPGAs||
Altera provides instructor-led and online classes to help you successfully design with Altera products. Here are some classes you can take:
Instructor-Led (click here for the full list):
- The Quartus II Software Design Series: Foundation
- Introduction to the Qsys System Integration Tool
- Advanced Qsys System Integration Tool Methodologies
- Building Gigabit Interfaces in Altera Transceiver Devices
- Parallel Computing with OpenCL
- Designing with DSP Builder Advanced Blockset
- Optimizing OpenCL for Altera FPGAs
Online (click here for the full list):
- What’s New in the Quartus II Software Version 13.1 (30 minutes)
- Introduction to Qsys (1.5 hours)
- Advanced System Design Using Qsys (1.5 hours)
- Introduction to Parallel Computing with OpenCL (30 minutes)
- Writing OpenCL Programs for Altera FPGAs (1 hour)
- Running OpenCL on Altera FPGAs
- SoC Hardware Overview Part 1 (1 hour) and Part 2 (30 min)
- Hardware Design Flow for an ARM-based SoC (1 hour)
- Software Design Flow for an ARM-based SoC (1 hour)
- Transceiver Toolkit (30 min)
Both the free Quartus II Web Edition software and Quartus II Subscription Edition software are available for download.
The Quartus II Web Edition software and ModelSim®-Altera Starter Edition simulation tool do not require a license file.
The Quartus II Subscription Edition software includes a free 30-day trial, and will require a license after the 30-day period. The annual software subscription is $2,995 for a node-locked PC license and is available for purchase at Altera's eStore.
The Quartus II Subscription Edition software includes:
- The Quartus II software
- The ModelSim-Altera Starter edition
- A full license to the IP Base Suite, which includes 15 of Altera’s most popular IP, including DSP and memory cores
Follow these three steps to get started:
- Download the Quartus II software with the new and improved Quartus II software installer
- Download the Quartus II Subscription Edition software (includes free 30-day trial)
- Download the Quartus II Web Edition software (free and no license required)
- Install the Quartus II software
- Start evaluation