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Design and Support Resources Guide

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This guide highlights and explains Altera's online design and support resources. The information is divided into four main sections to quickly guide you to resources that can help you with your product development.

Read Me First Read Me First! – Getting Started with Altera
  • Read Me First Read Me First! – Getting Started with Altera

  • A starting place to quickly understand and use Altera products, collateral, and resources — available in a half hour Online Course or a PDF version of the training. The information is divided into 5 sections which correspond to a typical design cycle. You will learn how to find and navigate key resources available to get your design to market as fast as possible.

Research Research
  • Research Research

  • Information to help you select the right devices and development tools

      • Product Literature

      • Our literature and technical documentation section lists handbooks (that include data sheets), application notes, user guides, manuals, pin connection guidelines, pin-out files, errata sheets, release notes, reliability reports, and more. You'll find product information, like our product selector guides, end market and corporate literature, as well as documentation on our FPGA, CPLD, and ASIC devices and our development software, intellectual property (IP) cores, and technology.   You can also request literature services such as subscriptions to weekly technical updates on new or changed documents, eNewsletters, and email announcements for updates on Altera® products, training, upcoming events, and more.

      • Devices

      • Product information on each Altera device series. You can use the left column navigation bar to see a summary of features and capabilities and descriptions about each device series. Or you can select a family in the series from the listings on the page. For example, you can view the About Stratix® Series page or go directly to information on the Stratix IV FPGA family.

        With Altera's Product Selector tool, perform a parametric search to filter your FPGA, CPLD, and ASIC device selection, and then compare features and specifications to help select the proper device for your application.

      • Webcasts

      • Short view-on-demand presentations about our FPGA, CPLD, and ASIC devices, industry topics, and related design software and IP.

      • Example Designs

      • Ready-to-use design examples to deliver efficient solutions to design problems. Use these examples to instantiate individual building blocks for use in a system design. For example, variations of external memory controller applications targeting Stratix and Cyclone® FPGA families. Additional design examples can be found as associated with application notes and user guides.

        An index of complete system reference designs using Altera IP cores and tools: PCIe, SRIO, SDI, Triple-Speed Ethernet and other high-speed interfaces, memory controllers, embedded processors, and digital signal processing (DSP). Downloadable with an myAltera account. Please log in to access

      • End Market Solutions

      • High-level, end market solutions for automotive, computer and storage, industrial, military, wireless, broadcast, consumer, medical, test and measurement, and wireline applications.

      • IP

      • A searchable database of Altera IP cores, related development kits, and reference designs, along with IP certification and licensing information. Get system-centric IP applications and design information, including IP related to embedded processors, DSP, and interface protocols from Altera's IP Resource Center.  For a free in-system evaluation of Altera and partner IP, see AN 320: OpenCore Plus Evaluation of Megafunctions (PDF). You can also use the transceiver protocol support selector guide to help select the right device for a chosen application.

        With Altera's Product Selector tool, perform a search to find the IP for your application.

      • System Building

      • Design embedded systems with the Quartus II development software and SOPC Builder tool. Build and simulate DSP systems using MathWorks/Simulink-to-FPGA DSP Builder design tool.

      • Development Kits

      • Wide range of Altera and Partner development kits to address a variety of applications.  Many development kits feature a standard host interface that accepts high-speed mezzanine cards (HSMC) daughter cards.  Applications include PCIe®, Ethernet, DVI, and more.

        With Altera's Product Selector tool, perform a search to find the development kit for your application.

      • Design and Support Services

      • Learn about Altera and Partner Professional design services to assist you in your product design.

      • Buy Online

      • Online store for Altera devices, tools, development kits, programming hardware, and cables.

Downloads and Training
  • Downloads and Training

  • Prepare to design with Altera®  products.

      • Download Center

      • Download Quartus® II software tools (latest and legacy), Nios® II Embedded Design Suite, ModelSim®-Altera, intellectual property (IP), license daemons, Gerber files and PCB footprints, SPICE and IBIS models, device programming software, and more.

      • Get a License

      • Review licensing options and get a license for software, intellectual property (IP), and development kits for products you have downloaded or purchased from Altera.   Requires a myAltera account to access. Please log in to access

      • Installation and Licensing Support

      • A central repository for installation and licensing support documentation. Refer to Altera Software Installation and Licensing (PDF) or use the licensing troubleshooter as a step-by-step diagnostic tool.

      • Altera Training Resources

      • Choose the training format, topic, and location. Use search courses to focus your selection. You can also view training partners outside of North America.  Note, a myAltera account is required to register for courses.  Please log in to access

          • Training Curricula

          • Series of courses for targeted designers – FPGA, CPLD, ASIC, embedded systems, ASIC-to-FPGA, digital signal processing (DSP), and system-on-a-chip (SOC).

          • Online Training (Free)

          • Review the technical training catalog for free online training on topics ranging from tool usage to digital signal processing (DSP) filters, DDR implementation, and more.

          • Online Demonstration Center (Free)

          • An online demonstration center providing quick, free demonstrations to introduce Quartus® II software tools and Nios® II Processor embedded tools to new users.

Design Resources
  • Design Resources

  • Help for every phase of product development

      • Design Phase
          • Design Flows

          • An overview of the design flow for FPGA, CPLD, and digital signal processing (DSP), and also how to get started with Nios® II processor and Nios II Embedded Design Suite (EDS) development tools.

          • System Design Tools

          • Reference materials and support for Nios II embedded processing systems, SOPC Builder, and DSP support including links to development kits and reference designs.

          • Quartus II Design Checklist

          • Thorough checklist for design planning, implementation, optimization and timing closure, I/O planning and constraints, PowerPlay early power estimator (EPE), Quartus® II PowerPlay power analysis and optimization, and on-chip debug (OCD).

          • Pin Connections
              • Pin-Out Files for Altera Devices

              • Files listing Altera device pin-out descriptions. There are up to three types of files for each device: Portable Document Format Files (.pdf), Text Files (.txt), and Microsoft Excel Files (.xls).

              • Device Pin Connections Guidelines

              • Altera recommended pin connections for each device. Note:  You need to apply simulation results to the design to verify proper device functionality.

              • Schematic Review Worksheets

              • Schematic Review Worksheets for selected Stratix® II, Stratix III, Stratix IV, Cyclone® III, and Arria® II FPGAs to assist you in reviewing schematics and tracking deviations from Altera's Device Pin Connections Guidelines.

          • Board Design and Signal Integrity
              • Power Management Resources

              • Power management resources for estimating power at various stages of your design.  PowerPlay EPE tools are for use before or during the design process to estimate power usage.  The PowerPlay power analyzer tools are for accurate power estimation after the design is complete.

              • Power Distribution Network (PDN) Tool

              • Graphical tool used with all Altera FPGAs to optimize the board-level PDN.  Link includes a dedicated PDN tool for Stratix IV FPGAs.

              • Board Design Guidelines

              • Consolidated information on all aspects of board design, including transceiver design, PDN, power dissipation and thermal management, simultaneous switching noise (SSN), PCB layout, signal integrity, JTAG debugging and configuration, external memory controllers, and more.

              • Device Layout Review Worksheets

              • Device Layout Review Worksheets are available for Altera transceiver-based devices to guide your PCB layout in following Altera’s recommendation – a great tool for your PCB layout design review. Note: These worksheets contain transceiver device specific information such as power rail voltage specifications, but they can also be used as a general guideline for non-transceiver devices in that family.

              • Board Design and I/O Resources

              • Board design resources and I/O management for users of the Quartus II development software tools.

              • Signal Integrity Center

              • IBIS Models, SPICE Models, board-level and device-level signal integrity tools, SSN estimator, training, and partners.

          • Phase-Locked Loop (PLL) Management

          • Summary and comparison matrix of PLL resources and features available in Stratix and Cyclone device families.

          • HardCopy Design

          • Summary and comparison matrix of HardCopy series ASICs and links to the Hardcopy IV ASIC family available with 6.5+ Gbps transceivers.

      • Implementation Phase
          • Configuration and Programming

          • Summary of the configuration schemes supported by Altera devices and links to all resources and reference materials.

          • Design Entry and Planning

          • Guidelines on planning and structuring your design, as well as details about managing metastability in your design, and HDL coding styles.

          • Advanced Synthesis Cookbook

          • PDF containing a collection of circuit building blocks and related discussions. Download also the advanced synthesis design files from manuals.

          • Synthesis and Netlist Viewers

          • Altera and third-party synthesis tools.

          • Scripting

          • Comprehensive command-line and Tcl design flows.

          • Incremental Compilation

          • How to use incremental compilation to segment your design into logical design partitions allowing top-down and bottom up design methodologies.  Save compilation time in top-down and facilitate team work in bottom-up.

          • Design Optimization

          • Optimize a design for area and timing.  Resources to help with design optimization, physical synthesis, and the Design Space Explorer (DSE).

          • Timing Analysis
              • TimeQuest

              • The static timing analyzer, TimeQuest, supports the industry-standard Synopsys Design Constraints (.sdc) format.  Use the Quartus II TimeQuest Timing Analyzer Cookbook (PDF) for a collection of scenarios, guidelines, and recommendations.

              • Switching to TimeQuest (PDF)

              • Benefits and process of Switching to the Quartus II TimeQuest Timing Analyzer (PDF) from the Quartus II Classic Timing Analyzer.

      • Verification Phase
          • On-Chip Debug

          • A resource center for tools that allow real-time capture of internal nodes in your design.  Plus Quick Design Debugging Using Signal Probe (PDF) and Design Debugging Using the SignalTapTM II Embedded Logic Analyzer (PDF).

Support Help Support Help
  • Support Help Support Help

  • Troubleshoot common problems.

      • Knowledge Database (KDB)

      • Most recent solutions, known issues, troubleshooters, and self-help tools. Also access to advanced search, search tips, and the KDB Browser to search solutions by product category, area, and sub-area.

      • Troubleshooters

      • Step-by-step diagnostic tools to solve common technical problems, including licensing, ModelSim®  software simulation, timing analysis, PLL loss of lock, FPGA configuration, JTAG configuration and ISP, parallel flash loader (PFL), Jam, JBC and SVF programming.

      • Altera Forum

      • The Altera Forum (www.alteraforum.com) brings Altera users together to learn from each other.  At the forum, you can share projects, news, and ideas related to Altera® products.

      • Altera Wiki

      • The Altera Wiki (www.alterawiki.com) is a community site for Altera users to collaborate on user guides, design tips, and frequently asked questions.

      • Design and Support Services

      • Learn about the professional design and support services offered by Altera and Altera partners.

      • mySupport

      • Submit a service request (SR) to an applications engineer.  Requires and Altera.com account to access. Please log in to access

      • Contacting Altera

      • Altera contact information, including sales offices, distributors and representatives, plus corporate office addresses, telephone numbers, and email addresses.

NOTE:

  1. Please log in to access Indicates a myAltera account is required to access the information.

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