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Device Support

Home > Support > Devices

Download the Arria™ GX Handbook

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Altera provides the following device support.

FPGAs
  • Stratix® V 
  • Stratix IV
  • Stratix III
  • Stratix II and Stratix II GX
  • Stratix and Stratix GX
  • Arria® V
  • Arria II
  • Arria GX
  • Cyclone® V 
  • Cyclone IV
  • Cyclone III
  • Cyclone II
  • Cyclone
CPLDs
  • MAX® V New
  • MAX II
  • MAX 3000A
  • MAX 7000
ASICs
  • HardCopy® IV
  • HardCopy III
  • HardCopy II
  • HardCopy Stratix
  • HardCopy APEX™
Downloads
  • Device Pin-Outs
  • Boundary-Scan Description Language (BSDL) and Boundary-Scan Test (BST)
  • SPICE Models
  • IBIS Models
  • Schematic Review Worksheets
  • Layout Review Worksheets 
  • Cadence Printed Circuit Board (PCB) Libraries
  • Mentor Graphics Printed Circuit Board (PCB) Libraries
  • Gerber Files
  • Literature
Configuration and Programming
  • Programming Center
  • Programming Tools
  • Configuration Center
    • Configuration via Protocol (CvP)
    • FPGA Configuration Schemes
Power Management
  • Power Management
  • Early Power Estimators
  • Certified Power Solutions
I/O
  • I/O FeaturesNew
  • I/O Specifications
  • Hot Socketing
PLL and Clock Management
  • Overview
  • Phase-Locked Loop (PLL) Basics
  • Using PLLs in Software
  • Jitter Information
  • Clock Networks
  • Glossary
  • Possible Causes for PLL Loss of Lock
  • PLL Loss of Lock Checklist
Packaging and Board Design
  • Package and Thermal Resistance
  • Package Drawing Search
  • Layouts and Sockets
  • Manufacturing
Failure Analysis
  • Failure Analysis Overview
  • Failure Analysis Capabilities
ECCN
  • Product ECCN Search
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  • FPGAs
    • Stratix V (E, GX, GS, GT)
    • Stratix IV (E, GX, GT)
    • Stratix III
    • Stratix II/Stratix II GX
    • Stratix/Stratix GX
    • Arria 10
    • Arria V (GX, GT, GZ, SX, ST)
    • Arria II (GX and GZ)
    • Arria GX
    • Cyclone V (E, GX, GT, SE, SX, ST)
    • Cyclone IV (E and GX)
    • Cyclone III
    • Cyclone II
    • Cyclone
  • CPLDs
    • MAX V
    • MAX II
    • MAX 3000A
    • MAX 7000
  • ASICs
    • HardCopy IV
    • HardCopy III
    • HardCopy II
    • HardCopy Stratix
    • HardCopy APEX
  • Downloads
    • Device Pin-Outs
    • BSDL Models
    • SPICE Models
    • IBIS Models
    • Schematic Review Worksheets
    • Layout Review Worksheets
    • Cadence PCB Libraries
    • Mentor Graphics PCB Libraries
    • Gerber Files
  • Configuration/Programming
    • Configuration
      • Schemes
        • AP
        • AS
        • FPP
        • JTAG
        • PPA
        • PPS
        • PS
      • Comparison
      • Features
      • Solutions
    • Programming
      • MAX II
      • MAX 3000A
      • MAX 7000
      • Configuration Devices
    • Programming Tools
      • Altera Programming Tools
        • Download Cables
        • Altera Programming Unit
        • Altera Programming SW
      • In-Circuit Testers
        • ICT Vendors
      • Boundary-Scan Tools
        • Vendor Support
      • Third Party
      • IEEE 1532
      • Jam STAPL
        • Embedded Programming
        • Vendor Support
  • Power
    • Power Management
      • Overview
      • Thermal Management
      • Power Supply Integrity
      • Power Supply Regulation
    • Early Power Estimators
    • Certified Power Solutions
  • I/O
    • Features
    • Specifications
    • Hot Socketing
  • PLL & Clock Management
    • Overview
    • PLL Basics
    • Using PLLs in Software
    • Jitter Information
    • Clock Networks
    • Glossary
  • Packaging & Board Design
    • Package and Thermal Resistance
    • Sockets and Layout
    • Manufacturing
  • Failure Analysis
    • Overview
    • Capabilities
  • ECCN
    • Product ECCN Search
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