Design Examples

All Design Examples

Altera and its partners develop design examples that provide the building blocks to help you better understand and easily use Altera products, implement various functions, and address basic design needs.

Refer to the Reference Designs section for more complex designs to help you address your design needs.

Available design examples can be found in the table below. For more details on each of the design examples, click the design example name in the Design Examples column. To narrow down your search, click the categories on the left navigation bar to sort the design examples by their functions or use the search box on the main Design Examples page to search by product descriptions or keywords.

Design Examples	Device Targeted	Development Kits Supported	SOPC Builder Ready	Qsys Compliant	Quartus II Version
Achieving Unity Gain in Block Floating Point IFFT+FFT Pair	-	-	-	-	9.1
Auto Start Using MAX II CPLDs: AN 491 (PDF)	MAX II	-	-	-	-
Avalon-MM Master Templates	-	-		-	8.0
Avalon-MM Slave Template	-	-		-	9.0
CF+ Interface MAX II CPLDs: AN 492 (PDF)	MAX II	-	-	-	10.0
CIC Interpolation Filter With Multi-Channel Data Support	-	-	-	-	-
Coefficient Reload Finite Impulse Response (FIR) Filter	-	-	-	-	9.1
Constraint RGMII Interface of Triple Speed Ethernet with the External PHY Delay Feature	Cyclone II, Cyclone III, Cyclone III LS, Cyclone IV GX, Stratix II, Stratix II GX, Stratix III, Stratix IV, Arria GX, Arria II GX	Stratix IV GX FPGA Development Kit, Arria II GX FPGA Development Kit	-	-	10.1
DDR2: 8-Bit Wide DDR2 ALTMEMPHY-Based SOPC Builder Integrated in Cyclone III FPGAs	Cyclone III	Cyclone III FPGA Development Kit		-	9.1
DDR2: Interfacing a 267-MHz DDR2 SDRAM with an Arria II GX FPGA	Arria II GX	Arria II GX FPGA Development Kit	-	-	9.1
DDR3: 8-Bit Wide DDR3 UniPHY-Based QSYS Integrated in Stratix IV FPGAs (Verilog)	Stratix IV GX	Audio Video Development Kit, Stratix IV GX Edition	-		11.0
DDR3: Interfacing a 300-MHz DDR3 SDRAM with an Arria II GX FPGA	Arria II GX	Arria II GX FPGA Development Kit	-	-	9.1
DDR3: Interfacing with a 64-bit DDR3 SDRAM UDIMM interface at 400 MHz in a Stratix IV FPGA	Stratix IV E	Stratix IV GX FPGA Development Kit	-	-	9.1
Designing Digital Down Conversion Systems Using CIC and FIR Filters	-	-	-	-	7.1
Fast Fourier Transform (FFT) with 32K-Point Transform Length	-	-	-	-	-
GPIO Pin Expansion Using I2C Bus Interface in MAX II CPLDs: AN 494 (PDF)	MAX II	-	-	-	-
HiSPi Design Example	Cyclone II, Cyclone V	-	-		12.1
I2C Battery Gauge Interface Using MAX II CPLDs: AN 493 (PDF)	MAX II	-	-	-	-
IDE/ATA Controller Using MAX II CPLDs: AN 495 (PDF)	MAX II	MDN-B2	-	-	10.0
Implementing an SMBus Controller MAX II CPLDs: AN 502 (PDF)	MAX II	-	-	-	10.0
Implementing LED Drivers in MAX & MAX II Devices: AN 286 (PDF)	MAX II	-	-	-	-
Implementing Multiple Memory Interface using UniPHY in a Stratix IV FPGA (Verilog)	Stratix IV E	Stratix IV E FPGA Development Kit	-	-	10.1
Implementing Multiple Memory Interface Using UniPHY in a Stratix V FPGA	Stratix V GX	-	-	-	11.0
Implementing OFDM Modulation and Demodulation	-	-	-	-	7.2
Interfacing with a 64-bit DDR3 SDRAM UniPHY Interface at 533 MHz in a Stratix IV FPGA	Stratix IV GX	Stratix IV GX FPGA Development Kit	-	-	11.0
LCD Controller Using MAX II CPLDs: AN 497 (PDF)	MAX II	-	-	-	-
LED Blink Using Auto Stop and Auto Start in MAX II CPLDs: AN 498 (PDF)	MAX II	MDN-B2	-	-	10.0
MAX II CPLDs as Voltage Level Shifters: AN 490 (PDF)	MAX II	-	-	-	-
Microcontroller I/O Expander	MAX 3000A	-	-	-	-
Mobile SDRAM Interface Using MAX II CPLDs: AN 499 (PDF)	MAX II	-	-	-	-
Multi-Channel Farrow Filter	-	-	-	-	-
Multiplexing SDIO Devices using MAX II CPLDs: AN 509 (PDF)	MAX II	-	-	-	-
NAND Flash Memory Interface with MAX II CPLDs: AN 500 (PDF)	MAX II	-	-	-	-
Nios II: 3C120 Microprocessor System with LCD Controller	Cyclone III	Cyclone III Edition, Altera Embedded Systems Development Kit, Cyclone III Edition		-	8.1
Nios II: 3C25 Microprocessor System with LCD Controller	Cyclone III	Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition		-	8.0
Nios II: Accelerated FIR with Built-In Direct Memory Access	Cyclone III, Stratix II	Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition, Altera Embedded Systems Development Kit, Cyclone III Edition, Nios II Development Kit, Stratix II Edition		-	9.0
Nios II: Alternative Nios II Boot Methods	Stratix IV GX, Cyclone III	Stratix IV GX FPGA Development Kit, Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition, Altera Embedded Systems Development Kit, Cyclone III Edition	-		12.0
Nios II: Altia Red Touch Screen HMI for D/AVE	Cyclone III	Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition		-	9.1
Nios II: Application Selector	Cyclone III	Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition, Altera Embedded Systems Development Kit, Cyclone III Edition	-		11.0
Nios II: Applications Processor MMU Design	Cyclone III, Stratix IV GX	Altera Embedded Systems Development Kit, Cyclone III Edition, Stratix IV GX FPGA Development Kit		-	10.1
Nios II: Avalon Verification IP Suite Design Example	-	-			11.0
Nios II: Board Diagnostic	Stratix II	Nios II Development Kit, Stratix II		-	10.0
Nios II: C2H Mandelbrot	Cyclone III	Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition, Altera Embedded Systems Development Kit, Cyclone III Edition		-	8.1
Nios II: Checksum Hardware Accelerator	Cyclone III	Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition		-	10.0
Nios II: Compact Configuration Design Example	Cyclone III	Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition, Altera Embedded Systems Development Kit, Cyclone III Edition		-	8.1
Nios II: Count Binary	Stratix II	Nios II Development Kit, Stratix II		-	10.0
Nios II: Custom CRC Accelerator	Stratix II	Nios II Development Kit, Stratix II		-	7.2
Nios II: Custom Instruction Design Example	Cyclone III, EP4S	Embedded Systems Development Kit, Cyclone III Edition, Nios II Embedded Evaluation Kit, Cyclone III Edition, Stratix IV GX FPGA Development Kit			11.0
Nios II: Debugging Nios II Systems with the SignalTap II Embedded Logic Analyzer	Cyclone III, Stratix IV GX	Embedded Systems Development Kit, Cyclone III Edition, Nios II Embedded Evaluation Kit, Cyclone III Edition, Stratix IV GX FPGA Development Kit	-		11.0
Nios II: Debugging with System Console over TCP/IP	Cyclone III	Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition		-	12.0
Nios II: Dhrystone Benchmark	Stratix II	Altera Embedded Systems Development Kit, Cyclone III Edition, Nios II Development Kit, Stratix II		-	8.0
Nios II: Ethernet Acceleration	Stratix IV GX	Stratix IV GX FPGA Development Kit			12.1
Nios II: Ethernet Standard Design	Cyclone III, Stratix IV GX	Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition, Altera Embedded Systems Development Kit, Cyclone III Edition, Stratix IV GX FPGA Development Kit	-		11.0
Nios II: HAL Device Drivers	Cyclone III	Nios II Embedded Evaluation Kit, Cyclone III Edition	-		11.0
Nios II: Hardware Development Tutorial Design Example	-	-	-		11.0
Nios II: Hello MicroC/OS-II	Stratix II	Nios II Development Kit, Stratix II		-	10.0
Nios II: High-Performance Example with Bridges	Stratix II	Nios II Development Kit, Stratix II		-	7.2
Nios II: IMAGEM Technology Solution Demos	Cyclone III	Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition		-	9.1
Nios II: Low Power	Cyclone III	Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition, Altera Embedded Systems Development Kit, Cyclone III Edition		-	8.0
Nios II: Memory Test	Stratix II	Nios II Development Kit, Stratix II		-	10.0
Nios II: Micrium µC/GUI Demo	Cyclone III	Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition		-	9.1
Nios II: MicroC/OS-II Message Box	Stratix II	Nios II Development Kit, Stratix II		-	10.0
Nios II: MicroC/OS-II Mutex	Stratix II	Nios II Development Kit, Stratix II		-	10.0
Nios II: MicroC/OS-II RTOS with the Nios II Processor	Cyclone III	Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition	-		11.0
Nios II: MPU Usage	Cyclone III	Nios II Embedded Evaluation Kit, Cyclone III Edition		-	9.1
Nios II: Multiprocessor Design Example	Cyclone III	Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition	-		11.0
Nios II: NTP Client	Cyclone III, Stratix II	Stratix IV GX FPGA Development Kit, Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition, Altera Embedded Systems Development Kit, Cyclone III Edition, Nios II Development Kit, Stratix II Edition		-	9.1
Nios II: Planetweb SpectraWorks Digital Photo Frame	Cyclone III	Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition		-	9.1
Nios II: Planetweb SpectraWorks GUI Feature Demo	Cyclone III	Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition		-	9.1
Nios II: Profiling Nios II Systems	Cyclone III, Stratix IV GX	Embedded Systems Development Kit, Cyclone III Edition, Nios II Embedded Evaluation Kit, Cyclone III Edition, Stratix IV GX FPGA Development Kit	-		11.0
Nios II: Read-Only Zip File System	Stratix II	Nios II Development Kit, Stratix II		-	10.0
Nios II: Simple Socket Server	Stratix II	Nios II Development Kit, Stratix II		-	10.0
Nios II: Simulating Nios II Embedded Processor Designs	Stratix II	Nios II Development Kit, Stratix II	-		11.0
Nios II: SPI Slave to Avalon Master	Cyclone III	Altera Embedded Systems Development Kit, Cyclone III Edition		-	9.1
Nios II: System Architect Design Example	Cyclone III	Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition	-		11.0
Nios II: TES D/AVE Graphics Accelerator Demo	Cyclone III	Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition		-	9.1
Nios II: Tightly Coupled Memory Tutorial	Cyclone III, Stratix IV GX	Embedded Systems Development Kit, Cyclone III Edition, Nios II Embedded Evaluation Kit, Cyclone III Edition, Stratix IV GX FPGA Development Kit	-		12.0
Nios II: Triple-Speed Ethernet Processor System	Cyclone III	Altera Embedded Systems Development Kit, Cyclone III Edition, Stratix IV GX FPGA Development Kit		-	10.1
Nios II: Using the NicheStack TCP/IP Stack	Cyclone III, Stratix IV GX	Embedded Systems Development Kit, Cyclone III Edition, Nios II Embedded Evaluation Kit, Cyclone III Edition, Stratix IV GX FPGA Development Kit	-		12.0
Nios II: Vectored Interrupt Controller Usage and Applications	Cyclone III	Nios II Embedded Evaluation Kit, Cyclone III Edition		-	9.1
Nios II: Web Server	Cyclone III	Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition		-	7.2
PCI Master Memory Example for pci_mt32 MegaCore Function	-	-	-	-	All
PCI Target Memory Examples for PCI MegaCore functions	-	-	-	-	All
PCI Target Termination Examples for pci_mt32 and pci_t32 MegaCore Functions	-	-	-	-	All
Polyphase Modulation With Aliasing for Digital Up-Conversion	-	-	-	-	-
POS-PHY Level 4 (SPI-4.2) External PLL Sharing Design Example	Stratix IV GX	-	-	-	9.1
Power Management in Portable Systems Using MAX II CPLDs: AN 422 (PDF)	MAX II	-	-	-	-
Pulse Width Modulator Using MAX II CPLDs: AN 501 (PDF)	MAX II	-	-	-	-
QDRII: Interfacing 400-MHz QDR II+ SRAM in a Stratix IV FPGA	Stratix IV E	Stratix IV GX FPGA Development Kit	-	-	11.0
RapidIO: Maintenance Master to System Maintenance Slave Bridge	-	-	-	-	All
Reconfigurable Decimation Filter	-	-	-	-	-
RLDRAMII: Interfacing 533-MHz RLDRAM II in a Stratix IV FPGA	Stratix IV E	Stratix IV E Development Kit	-	-	11.0
Run-Time Reconfigurable Scaler Design Example	Stratix II, Cyclone II	-		-	9.0
Serial Peripheral Interface (SPI) Master in MAX II CPLDs: AN 485 (PDF)	MAX II	-	-	-	7.2
Sigma-Delta Converter	-	-	-	-	-
SMBus for GPIO Pin Expansion in MAX II CPLDs: AN 484 (PDF)	MAX II	MDN-B2	-	-	-
SPI to I2C Using MAX II CPLDs: AN 486 (PDF)	MAX II	-	-	-	-
SPI to I2S Using MAX II CPLDs: AN 487 (PDF)	MAX II	-	-	-	10.0
Stepper Motor Controller Using MAX II CPLDs: AN 488 (PDF)	MAX II	MDN-B2	-	-	7.2
TSE: Implement Reset Sequence in TSE Using ALTGX as Transceiver	Stratix IV GX	-	-	-	9.1 SP1
TSE: Implement Reset Sequence in TSE Using ALTLVDS as Transceiver	Stratix IV GX	-	-	-	9.1 SP1
TSE: Instantiate TSE with External ALTGX / ALTLVDS	Stratix IV GX, Arria II GX	-		-	9.1 SP1
Using CIC Decimation Filter With Multi-Channel Support	-	-	-	-	7.2
Using the Internal Oscillator in MAX II CPLDs: AN 496 (PDF)	MAX II	MDN-B2	-	-	7.2
Using the Parallel Flash Loader with the Quartus II Software: AN 386 (PDF)	MAX II	-	-	-	10.0
Using the UFM in MAX II Devices: AN 489 (PDF)	MAX II	-	-	-	-
Variable Rate Decimation Filter	-	-	-	-	-

Design Examples Disclaimer

These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an "as-is" basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.