All Design Examples
Altera and its partners develop design examples that provide the building blocks to help you better understand and easily use Altera products, implement various functions, and address basic design needs.
Refer to the Reference Designs section for more complex designs to help you address your design needs.
Available design examples can be found in the table below. For more details on each of the design examples, click the design example name in the Design Examples column. To narrow down your search, click the categories on the left navigation bar to sort the design examples by their functions or use the search box on the main Design Examples page to search by product descriptions or keywords.
Design Examples
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Device Targeted | Development Kits Supported | SOPC Builder Ready ![]() ![]() |
Qsys Compliant ![]() ![]() |
Quartus II Version ![]() ![]() |
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Achieving Unity Gain in Block Floating Point IFFT+FFT Pair
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- | - | - | - | 9.1 |
Auto Start Using MAX II CPLDs: AN 491 (PDF)
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- | - | - | - |
Avalon-MM Master Templates
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- | - | ![]() |
- | 8.0 |
Avalon-MM Slave Template
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- | - | ![]() |
- | 9.0 |
CF+ Interface MAX II CPLDs: AN 492 (PDF)
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- | - | - | 10.0 |
CIC Interpolation Filter With Multi-Channel Data Support
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- | - | - | - | - |
Coefficient Reload Finite Impulse Response (FIR) Filter
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- | - | - | - | 9.1 |
Cyclone II, Cyclone III, Cyclone III LS, Cyclone IV GX, Stratix II, Stratix II GX, Stratix III, Stratix IV, Arria GX, Arria II GX |
Stratix IV GX FPGA Development Kit, Arria II GX FPGA Development Kit |
- | - | 10.1 |
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DDR2: 8-Bit Wide DDR2 ALTMEMPHY-Based SOPC Builder Integrated in Cyclone III FPGAs
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Cyclone III FPGA Development Kit |
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- | 9.1 |
DDR2: Interfacing a 267-MHz DDR2 SDRAM with an Arria II GX FPGA
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Arria II GX FPGA Development Kit |
- | - | 9.1 |
DDR3: 8-Bit Wide DDR3 UniPHY-Based QSYS Integrated in Stratix IV FPGAs (Verilog)
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Audio Video Development Kit, Stratix IV GX Edition |
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11.0 |
DDR3: Interfacing a 300-MHz DDR3 SDRAM with an Arria II GX FPGA
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Arria II GX FPGA Development Kit |
- | - | 9.1 |
DDR3: Interfacing with a 64-bit DDR3 SDRAM UDIMM interface at 400 MHz in a Stratix IV FPGA
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Stratix IV GX FPGA Development Kit |
- | - | 9.1 |
Designing Digital Down Conversion Systems Using CIC and FIR Filters
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- | - | - | - | 7.1 |
Fast Fourier Transform (FFT) with 32K-Point Transform Length
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- | - | - | - | - |
GPIO Pin Expansion Using I2C Bus Interface in MAX II CPLDs: AN 494 (PDF)
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- | - | - | - |
HiSPi Design Example
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Cyclone II, Cyclone V |
- | - | ![]() |
12.1 |
I2C Battery Gauge Interface Using MAX II CPLDs: AN 493 (PDF)
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- | - | - | - |
IDE/ATA Controller Using MAX II CPLDs: AN 495 (PDF)
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MDN-B2 |
- | - | 10.0 |
Implementing an SMBus Controller MAX II CPLDs: AN 502 (PDF)
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- | - | - | 10.0 |
Implementing LED Drivers in MAX & MAX II Devices: AN 286 (PDF)
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- | - | - | - |
Implementing Multiple Memory Interface using UniPHY in a Stratix IV FPGA (Verilog)
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Stratix IV E FPGA Development Kit |
- | - | 10.1 |
Implementing Multiple Memory Interface Using UniPHY in a Stratix V FPGA
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- | - | - | 11.0 |
Implementing OFDM Modulation and Demodulation
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- | - | - | - | 7.2 |
Interfacing with a 64-bit DDR3 SDRAM UniPHY Interface at 533 MHz in a Stratix IV FPGA
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Stratix IV GX FPGA Development Kit |
- | - | 11.0 |
LCD Controller Using MAX II CPLDs: AN 497 (PDF)
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- | - | - | - |
LED Blink Using Auto Stop and Auto Start in MAX II CPLDs: AN 498 (PDF)
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MDN-B2 |
- | - | 10.0 |
MAX II CPLDs as Voltage Level Shifters: AN 490 (PDF)
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- | - | - | - |
Microcontroller I/O Expander
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- | - | - | - |
Mobile SDRAM Interface Using MAX II CPLDs: AN 499 (PDF)
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- | - | - | - |
Multi-Channel Farrow Filter
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- | - | - | - | - |
Multiplexing SDIO Devices using MAX II CPLDs: AN 509 (PDF)
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- | - | - | - |
NAND Flash Memory Interface with MAX II CPLDs: AN 500 (PDF)
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- | - | - | - |
Nios II: 3C120 Microprocessor System with LCD Controller
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Cyclone III Edition, Altera Embedded Systems Development Kit, Cyclone III Edition |
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- | 8.1 |
Nios II: 3C25 Microprocessor System with LCD Controller
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Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition |
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- | 8.0 |
Nios II: Accelerated FIR with Built-In Direct Memory Access
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Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition, Altera Embedded Systems Development Kit, Cyclone III Edition, Nios II Development Kit, Stratix II Edition |
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- | 9.0 |
Nios II: Alternative Nios II Boot Methods
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Stratix IV GX FPGA Development Kit, Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition, Altera Embedded Systems Development Kit, Cyclone III Edition |
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12.0 |
Nios II: Altia Red Touch Screen HMI for D/AVE
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Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition |
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- | 9.1 |
Nios II: Application Selector
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Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition, Altera Embedded Systems Development Kit, Cyclone III Edition |
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11.0 |
Nios II: Applications Processor MMU Design
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Altera Embedded Systems Development Kit, Cyclone III Edition, Stratix IV GX FPGA Development Kit |
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- | 10.1 |
Nios II: Avalon Verification IP Suite Design Example
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- | - | ![]() |
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11.0 |
Nios II: Board Diagnostic
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Nios II Development Kit, Stratix II |
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- | 10.0 |
Nios II: C2H Mandelbrot
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Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition, Altera Embedded Systems Development Kit, Cyclone III Edition |
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- | 8.1 |
Nios II: Checksum Hardware Accelerator
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Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition |
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- | 10.0 |
Nios II: Compact Configuration Design Example
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Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition, Altera Embedded Systems Development Kit, Cyclone III Edition |
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- | 8.1 |
Nios II: Count Binary
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Nios II Development Kit, Stratix II |
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- | 10.0 |
Nios II: Custom CRC Accelerator
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Nios II Development Kit, Stratix II |
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- | 7.2 |
Nios II: Custom Instruction Design Example
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Embedded Systems Development Kit, Cyclone III Edition, Nios II Embedded Evaluation Kit, Cyclone III Edition, Stratix IV GX FPGA Development Kit |
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11.0 |
Nios II: Debugging Nios II Systems with the SignalTap II Embedded Logic Analyzer
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Embedded Systems Development Kit, Cyclone III Edition, Nios II Embedded Evaluation Kit, Cyclone III Edition, Stratix IV GX FPGA Development Kit |
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11.0 |
Nios II: Debugging with System Console over TCP/IP
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Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition |
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- | 12.0 |
Nios II: Dhrystone Benchmark
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Altera Embedded Systems Development Kit, Cyclone III Edition, Nios II Development Kit, Stratix II |
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- | 8.0 |
Nios II: Ethernet Acceleration
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Stratix IV GX FPGA Development Kit |
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12.1 |
Nios II: Ethernet Standard Design
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Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition, Altera Embedded Systems Development Kit, Cyclone III Edition, Stratix IV GX FPGA Development Kit |
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11.0 |
Nios II: HAL Device Drivers
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Nios II Embedded Evaluation Kit, Cyclone III Edition |
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11.0 |
Nios II: Hardware Development Tutorial Design Example
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- | - | - | ![]() |
11.0 |
Nios II: Hello MicroC/OS-II
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Nios II Development Kit, Stratix II |
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- | 10.0 |
Nios II: High-Performance Example with Bridges
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Nios II Development Kit, Stratix II |
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- | 7.2 |
Nios II: IMAGEM Technology Solution Demos
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Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition |
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- | 9.1 |
Nios II: Low Power
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Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition, Altera Embedded Systems Development Kit, Cyclone III Edition |
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- | 8.0 |
Nios II: Memory Test
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Nios II Development Kit, Stratix II |
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- | 10.0 |
Nios II: Micrium µC/GUI Demo
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Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition |
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- | 9.1 |
Nios II: MicroC/OS-II Message Box
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Nios II Development Kit, Stratix II |
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- | 10.0 |
Nios II: MicroC/OS-II Mutex
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Nios II Development Kit, Stratix II |
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- | 10.0 |
Nios II: MicroC/OS-II RTOS with the Nios II Processor
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Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition |
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11.0 |
Nios II: MPU Usage
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Nios II Embedded Evaluation Kit, Cyclone III Edition |
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- | 9.1 |
Nios II: Multiprocessor Design Example
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Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition |
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11.0 |
Nios II: NTP Client
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Stratix IV GX FPGA Development Kit, Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition, Altera Embedded Systems Development Kit, Cyclone III Edition, Nios II Development Kit, Stratix II Edition |
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- | 9.1 |
Nios II: Planetweb SpectraWorks Digital Photo Frame
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Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition |
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- | 9.1 |
Nios II: Planetweb SpectraWorks GUI Feature Demo
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Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition |
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- | 9.1 |
Nios II: Profiling Nios II Systems
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Embedded Systems Development Kit, Cyclone III Edition, Nios II Embedded Evaluation Kit, Cyclone III Edition, Stratix IV GX FPGA Development Kit |
- | ![]() |
11.0 |
Nios II: Read-Only Zip File System
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Nios II Development Kit, Stratix II |
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- | 10.0 |
Nios II: Simple Socket Server
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Nios II Development Kit, Stratix II |
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- | 10.0 |
Nios II: Simulating Nios II Embedded Processor Designs
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Nios II Development Kit, Stratix II |
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11.0 |
Nios II: SPI Slave to Avalon Master
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Altera Embedded Systems Development Kit, Cyclone III Edition |
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- | 9.1 |
Nios II: System Architect Design Example
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Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition |
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11.0 |
Nios II: TES D/AVE Graphics Accelerator Demo
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Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition |
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- | 9.1 |
Nios II: Tightly Coupled Memory Tutorial
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Embedded Systems Development Kit, Cyclone III Edition, Nios II Embedded Evaluation Kit, Cyclone III Edition, Stratix IV GX FPGA Development Kit |
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12.0 |
Nios II: Triple-Speed Ethernet Processor System
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Altera Embedded Systems Development Kit, Cyclone III Edition, Stratix IV GX FPGA Development Kit |
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- | 10.1 |
Nios II: Using the NicheStack TCP/IP Stack
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Embedded Systems Development Kit, Cyclone III Edition, Nios II Embedded Evaluation Kit, Cyclone III Edition, Stratix IV GX FPGA Development Kit |
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12.0 |
Nios II: Vectored Interrupt Controller Usage and Applications
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Nios II Embedded Evaluation Kit, Cyclone III Edition |
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- | 9.1 |
Nios II: Web Server
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Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition |
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- | 7.2 |
PCI Master Memory Example for pci_mt32 MegaCore Function
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- | - | - | - | All |
PCI Target Memory Examples for PCI MegaCore functions
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- | - | - | - | All |
PCI Target Termination Examples for pci_mt32 and pci_t32 MegaCore Functions
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- | - | - | - | All |
Polyphase Modulation With Aliasing for Digital Up-Conversion
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- | - | - | - | - |
POS-PHY Level 4 (SPI-4.2) External PLL Sharing Design Example
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- | - | - | 9.1 |
Power Management in Portable Systems Using MAX II CPLDs: AN 422 (PDF)
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- | - | - | - |
Pulse Width Modulator Using MAX II CPLDs: AN 501 (PDF)
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- | - | - | - |
QDRII: Interfacing 400-MHz QDR II+ SRAM in a Stratix IV FPGA
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Stratix IV GX FPGA Development Kit |
- | - | 11.0 |
RapidIO: Maintenance Master to System Maintenance Slave Bridge
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- | - | - | - | All |
Reconfigurable Decimation Filter
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- | - | - | - | - |
RLDRAMII: Interfacing 533-MHz RLDRAM II in a Stratix IV FPGA
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Stratix IV E Development Kit |
- | - | 11.0 |
Run-Time Reconfigurable Scaler Design Example
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- | 9.0 |
Serial Peripheral Interface (SPI) Master in MAX II CPLDs: AN 485 (PDF)
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- | - | - | 7.2 |
Sigma-Delta Converter
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- | - | - | - | - |
SMBus for GPIO Pin Expansion in MAX II CPLDs: AN 484 (PDF)
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MDN-B2 |
- | - | - |
SPI to I2C Using MAX II CPLDs: AN 486 (PDF)
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- | - | - | - |
SPI to I2S Using MAX II CPLDs: AN 487 (PDF)
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- | - | - | 10.0 |
Stepper Motor Controller Using MAX II CPLDs: AN 488 (PDF)
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MDN-B2 |
- | - | 7.2 |
TSE: Implement Reset Sequence in TSE Using ALTGX as Transceiver
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- | - | - | 9.1 SP1 |
TSE: Implement Reset Sequence in TSE Using ALTLVDS as Transceiver
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- | - | - | 9.1 SP1 |
TSE: Instantiate TSE with External ALTGX / ALTLVDS
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- | 9.1 SP1 |
Using CIC Decimation Filter With Multi-Channel Support
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- | - | - | - | 7.2 |
Using the Internal Oscillator in MAX II CPLDs: AN 496 (PDF)
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MDN-B2 |
- | - | 7.2 |
Using the Parallel Flash Loader with the Quartus II Software: AN 386 (PDF)
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- | - | - | 10.0 |
Using the UFM in MAX II Devices: AN 489 (PDF)
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Variable Rate Decimation Filter
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Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an "as-is" basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.