Interface Protocols
Interface protocols enable chip-to-chip, board-to-board, or box-to-box connectivity in system designs. Protocol intellectual property (IP) solutions from Altera and our partners satisfy the needs of a broad spectrum of applications and leverage the integrated transceivers in our FPGA and ASIC devices. Interface protocol solutions are delivered as licensable IP cores and reference designs as well as no-cost megafunctions and design examples.
Visit our Transceiver Protocols section to learn more about the integrated transceivers and their supporting interface protocol solutions.
Design Examples
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Device Targeted | Development Kits Supported | SOPC Builder Ready ![]() ![]() |
Qsys Compliant ![]() ![]() |
Quartus II Version ![]() ![]() |
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Cyclone II, Cyclone III, Cyclone III LS, Cyclone IV GX, Stratix II, Stratix II GX, Stratix III, Stratix IV, Arria GX, Arria II GX |
Stratix IV GX FPGA Development Kit, Arria II GX FPGA Development Kit |
- | - | 10.1 |
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GPIO Pin Expansion Using I2C Bus Interface in MAX II CPLDs: AN 494 (PDF)
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HiSPi Design Example
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Cyclone II, Cyclone V |
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12.1 |
I2C Battery Gauge Interface Using MAX II CPLDs: AN 493 (PDF)
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Implementing an SMBus Controller MAX II CPLDs: AN 502 (PDF)
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- | - | - | 10.0 |
Multiplexing SDIO Devices using MAX II CPLDs: AN 509 (PDF)
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- | - | - | - |
Nios II: Ethernet Acceleration
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Stratix IV GX FPGA Development Kit |
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12.1 |
Nios II: Ethernet Standard Design
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Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition, Altera Embedded Systems Development Kit, Cyclone III Edition, Stratix IV GX FPGA Development Kit |
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11.0 |
Nios II: SPI Slave to Avalon Master
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Altera Embedded Systems Development Kit, Cyclone III Edition |
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- | 9.1 |
Nios II: Triple-Speed Ethernet Processor System
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Altera Embedded Systems Development Kit, Cyclone III Edition, Stratix IV GX FPGA Development Kit |
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- | 10.1 |
Nios II: Web Server
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Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition |
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- | 7.2 |
PCI Master Memory Example for pci_mt32 MegaCore Function
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- | - | - | - | All |
PCI Target Memory Examples for PCI MegaCore functions
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- | - | - | - | All |
PCI Target Termination Examples for pci_mt32 and pci_t32 MegaCore Functions
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- | - | - | - | All |
POS-PHY Level 4 (SPI-4.2) External PLL Sharing Design Example
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- | - | - | 9.1 |
RapidIO: Maintenance Master to System Maintenance Slave Bridge
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- | - | - | - | All |
Serial Peripheral Interface (SPI) Master in MAX II CPLDs: AN 485 (PDF)
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- | - | - | 7.2 |
SMBus for GPIO Pin Expansion in MAX II CPLDs: AN 484 (PDF)
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MDN-B2 |
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SPI to I2C Using MAX II CPLDs: AN 486 (PDF)
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SPI to I2S Using MAX II CPLDs: AN 487 (PDF)
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- | - | - | 10.0 |
TSE: Implement Reset Sequence in TSE Using ALTGX as Transceiver
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- | - | - | 9.1 SP1 |
TSE: Implement Reset Sequence in TSE Using ALTLVDS as Transceiver
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- | - | - | 9.1 SP1 |
TSE: Instantiate TSE with External ALTGX / ALTLVDS
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- | 9.1 SP1 |
Using the Internal Oscillator in MAX II CPLDs: AN 496 (PDF)
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MDN-B2 |
- | - | 7.2 |
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an "as-is" basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.