Design Examples

Interface Protocols

Interface protocols enable chip-to-chip, board-to-board, or box-to-box connectivity in system designs. Protocol intellectual property (IP) solutions from Altera and our partners satisfy the needs of a broad spectrum of applications and leverage the integrated transceivers in our FPGA and ASIC devices. Interface protocol solutions are delivered as licensable IP cores and reference designs as well as no-cost megafunctions and design examples.

Visit our Transceiver Protocols section to learn more about the integrated transceivers and their supporting interface protocol solutions.

Design Examples	Device Targeted	Development Kits Supported	SOPC Builder Ready	Qsys Compliant	Quartus II Version
Constraint RGMII Interface of Triple Speed Ethernet with the External PHY Delay Feature	Cyclone II, Cyclone III, Cyclone III LS, Cyclone IV GX, Stratix II, Stratix II GX, Stratix III, Stratix IV, Arria GX, Arria II GX	Stratix IV GX FPGA Development Kit, Arria II GX FPGA Development Kit	-	-	10.1
GPIO Pin Expansion Using I2C Bus Interface in MAX II CPLDs: AN 494 (PDF)	MAX II	-	-	-	-
HiSPi Design Example	Cyclone II, Cyclone V	-	-		12.1
I2C Battery Gauge Interface Using MAX II CPLDs: AN 493 (PDF)	MAX II	-	-	-	-
Implementing an SMBus Controller MAX II CPLDs: AN 502 (PDF)	MAX II	-	-	-	10.0
Multiplexing SDIO Devices using MAX II CPLDs: AN 509 (PDF)	MAX II	-	-	-	-
Nios II: Ethernet Acceleration	Stratix IV GX	Stratix IV GX FPGA Development Kit			12.1
Nios II: Ethernet Standard Design	Cyclone III, Stratix IV GX	Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition, Altera Embedded Systems Development Kit, Cyclone III Edition, Stratix IV GX FPGA Development Kit	-		11.0
Nios II: SPI Slave to Avalon Master	Cyclone III	Altera Embedded Systems Development Kit, Cyclone III Edition		-	9.1
Nios II: Triple-Speed Ethernet Processor System	Cyclone III	Altera Embedded Systems Development Kit, Cyclone III Edition, Stratix IV GX FPGA Development Kit		-	10.1
Nios II: Web Server	Cyclone III	Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition		-	7.2
PCI Master Memory Example for pci_mt32 MegaCore Function	-	-	-	-	All
PCI Target Memory Examples for PCI MegaCore functions	-	-	-	-	All
PCI Target Termination Examples for pci_mt32 and pci_t32 MegaCore Functions	-	-	-	-	All
POS-PHY Level 4 (SPI-4.2) External PLL Sharing Design Example	Stratix IV GX	-	-	-	9.1
RapidIO: Maintenance Master to System Maintenance Slave Bridge	-	-	-	-	All
Serial Peripheral Interface (SPI) Master in MAX II CPLDs: AN 485 (PDF)	MAX II	-	-	-	7.2
SMBus for GPIO Pin Expansion in MAX II CPLDs: AN 484 (PDF)	MAX II	MDN-B2	-	-	-
SPI to I2C Using MAX II CPLDs: AN 486 (PDF)	MAX II	-	-	-	-
SPI to I2S Using MAX II CPLDs: AN 487 (PDF)	MAX II	-	-	-	10.0
TSE: Implement Reset Sequence in TSE Using ALTGX as Transceiver	Stratix IV GX	-	-	-	9.1 SP1
TSE: Implement Reset Sequence in TSE Using ALTLVDS as Transceiver	Stratix IV GX	-	-	-	9.1 SP1
TSE: Instantiate TSE with External ALTGX / ALTLVDS	Stratix IV GX, Arria II GX	-		-	9.1 SP1
Using the Internal Oscillator in MAX II CPLDs: AN 496 (PDF)	MAX II	MDN-B2	-	-	7.2

Design Examples Disclaimer

These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an "as-is" basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.