Altera® FPGAs provide abundant on-chip internal SRAM memory resources, but system bandwidth requirements often necessitate the use of large, fast off-chip memory devices. Memory controller intellectual property (IP) solutions from Altera and our partners include licensable cores, reference designs and design examples. All are hardware-tested drop-in design blocks that greatly simplify the local interface to complex memory devices.
Visit our External Memory section to learn more about interfacing with external memory.
|Device Targeted||Development Kits Supported||SOPC Builder Ready
||Quartus II Version
Mobile SDRAM Interface Using MAX II CPLDs: AN 499 (PDF)
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an "as-is" basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.