DDR3 Interfaces
Altera® FPGAs provide abundant on-chip internal SRAM memory resources, but system bandwidth requirements often necessitate the use of large, fast off-chip memory devices. Memory controller intellectual property (IP) solutions from Altera and our partners include licensable cores, reference designs and design examples. All are hardware-tested drop-in design blocks that greatly simplify the local interface to complex memory devices.
Visit our External Memory section to learn more about interfacing with external memory.
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Design Examples
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Device Targeted | Development Kits Supported | SOPC Builder Ready |
Qsys Compliant |
Quartus II Version |
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DDR3: 8-Bit Wide DDR3 UniPHY-Based QSYS Integrated in Stratix IV FPGAs (Verilog)
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Audio Video Development Kit, Stratix IV GX Edition |
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11.0 |
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DDR3: Interfacing a 300-MHz DDR3 SDRAM with an Arria II GX FPGA
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Arria II GX FPGA Development Kit |
- | - | 9.1 |
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DDR3: Interfacing with a 64-bit DDR3 SDRAM UDIMM interface at 400 MHz in a Stratix IV FPGA
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Stratix IV GX FPGA Development Kit |
- | - | 9.1 |
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Implementing Multiple Memory Interface Using UniPHY in a Stratix V FPGA
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- | - | - | 11.0 |
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Interfacing with a 64-bit DDR3 SDRAM UniPHY Interface at 533 MHz in a Stratix IV FPGA
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Stratix IV GX FPGA Development Kit |
- | - | 11.0 |
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an "as-is" basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
