Simulation
Altera provides a suite of verification intellectual property (IP) cores, such as bus functional models (BFMs), to simulate the behavior of Avalon® Memory-Mapped (Avalon-MM) master and slave interfaces and Avalon Streaming (Avalon-ST) source and sink interfaces. Verification components also include monitors to verify both Avalon protocols.
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Design Examples
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Device Targeted | Development Kits Supported | SOPC Builder Ready |
Qsys Compliant |
Quartus II Version |
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Nios II: Avalon Verification IP Suite Design Example
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- | - |  |
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11.0 |
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Nios II: Debugging with System Console over TCP/IP
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Nios II Embedded Evaluation Kit (NEEK), Cyclone III Edition |
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- | 12.0 |
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Nios II: Simulating Nios II Embedded Processor Designs
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Nios II Development Kit, Stratix II |
- | |
11.0 |
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an "as-is" basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
