Table 1 contains design examples demonstrating gate-level timing simulation of Altera® devices. Gate-level timing simulations are performed with Mentor Graphics® ModelSim® software to ensure that the post-synthesized or post-fit netlist passes the functional specifications.
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Table 1. Simulation Design Examples |
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Function |
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PLL Gate-Level Timing Simulation |
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Stratix® II GX Post-Fit Timing Simulation |
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ModelSim SE/PE Software (Verilog HDL) |
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ModelSim-Altera Software (Verilog HDL) |
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ModelSim SE/PE Software (VHDL) |
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ModelSim-Altera Software (VHDL) |
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Stratix II Post-Fit Timing Simulation |
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ModelSim SE/PE Software (Verilog HDL) |
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ModelSim-Altera Software (Verilog HDL) |
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ModelSim SE/PE Software (VHDL) |
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ModelSim-Altera Software (VHDL) |
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Stratix IV GX Post-Fit Timing Simulation |
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ModelSim SE/PE Software (Verilog HDL) |
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ModelSim-Altera Software (Verilog HDL) |
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ModelSim SE/PE Software (VHDL) |
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ModelSim-Altera Software (VHDL) |
Related Links
- ModelSim-Altera Software Support
- Simulation and Verification Resource Center
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.
