To get you started quickly on performing simulations with Cadence NC-Sim simulator, Altera offers a design example for use in designs for Altera® devices. The design example demonstrates gate-level timing simulation of Altera devices. The gate-level netlist and the Standard Delay Format (SDF) data for the design are produced from Quartus® II software after design compilation. Gate-level timing simulations of the netlist are performed with Cadence NC-Sim software to ensure that the synthesized netlist passes the functional specifications after the place and route (compilation) of your design.
Stratix® II Post-Fit Timing Simulation With Cadence NC-Sim Simulator
The following entry mode(s) are used in this example:
- Altera hardware description language (AHDL)
- MAX+PLUS® II Graphic Editor
- Verilog hardware description language (HDL)
- Tool command language (Tcl)
- Quartus II development tool
Design Examples Disclaimer
These design examples may only be used within Altera Corporation devices and remain the property of Altera. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.