These examples show a variety of techniques for constraining circuits and reporting timing analysis results in the TimeQuest timing analyzer.
These design examples show how to constrain different types of circuits for the TimeQuest timing analyzer.
Basic SDC Example
This example shows the simplest SDC file you can use that constrains all the clocks, input paths, and output paths in a design.
This example shows how to make multicycle exceptions with SDC commands. It includes a simple circuit with a multicycle exception of 2.
Constraining Generated Clocks
You must constrain generated clocks in your design. This example shows you how to constrain a divide by 2 clock and a phase-locked loop (PLL)-generated clock.
Clock Multiplexer Examples
This example shows how to constrain multiplexed clocks in your design.
Source Synchronous Center-Aligned Output
This example shows how to constrain a center-aligned source synchronous output bus.
Source Synchronous Edge-Aligned Output
This example shows how to constrain an edge-aligned source synchronous output bus.
Source Synchronous Center-Aligned Input
This example shows how to constrain a center-aligned source synchronous input bus.
Source Synchronous Edge-Aligned Input
This example shows how to constrain an edge-aligned source synchronous input bus.
Clock Enable Multicycle
This example shows how to apply a multicycle exception from a register feeding the clock enable pin of a register.
Clocks Feeding a Pin
This custom procedure gets a list of all clocks driving a pin in the timing netlist. Use it to create clocks dynamically when other clocks in the design are unknown.
Simplify Design Reuse with Dynamic SDC Constraints
Techniques to create timing constraints for reusable HDL blocks when their instantiation and use are not known by the designer.
These examples show how to perform different types of customized reporting.
Custom Timing Report Script
This example shows how to use the Tcl Script File for customizing reports during compilation to generate custom reports in the Quartus® II software Compilation Report.
Reporting Multiple Operating Conditions
This example shows how to perform a multicorner analysis on your design with a Tcl script.
Reporting Register to Register Paths
This example shows how to generate a register-to-register path report.
Reporting Point-to-Point Delays
This example shows how to report a delay for any point-to-point path.
Reporting Unconstrained Paths
This example shows how to generate an unconstrained path report.
Reporting Net Timing
This example shows how to generate a net timing delay report.
Reporting Failing Clock Analyses
This example shows how to report only failing clock analyses for all operating conditions.
Scripting and Entity and Instance Names
This example shows how to handle entity names in custom scripts that use get_registers, get_pins, and get_cells.
Reporting Levels of Logic
This example shows how to create a custom report that displays the number of levels of logic for sets of paths.
Design Examples Disclaimer
These design examples may only be used within Altera® devices and remain the property of Altera Corporation. They are being provided on an “as-is” basis and as an accommodation; therefore, all warranties, representations, or guarantees of any kind (whether express, implied, or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.