Triple-Speed Ethernet Data Path Reference Design

from Altera

Overview

Altera's Triple-Speed Ethernet (TSE) data path reference design provides a simple and quick way to implement your own Ethernet-based design in an Altera^® FPGA, and to observe live network traffic flowing through a loop-back Ethernet cable or a Gigabit Ethernet switch. This design also helps you to verify your Ethernet-based system operation with an Altera University of New Hampshire (UNH) verified TSE function and a standard off-the-shelf Ethernet PHY device. You can leverage this design to build your own Ethernet system with low risk and minimal effort.

The reference design is built with Altera's SOPC Builder using two instances of the Altera TSE MegaCore^® function in a Stratix^® II GX FPGA and two of the serial transceivers in the FPGA. This reference design demonstrates the operation of the TSE MegaCore function up to the maximum wire-speed performance in loop-back hardware configuration.

Features

• Showcases two instances of the Altera TSE MegaCore function supporting 10/100/1000 Mbps Ethernet operations in SGMII mode with auto-negotiation
• Demonstrates sending, receiving, and automatic checking of Ethernet packets up to the maximum theoretical data rates of 10/100/1000 Mbps 
• Jump-starts your embedded system design/performance evaluation
  • Minimal hardware requirements: Stratix II GX PCI Express development kit, two small form pluggable (SFP) modules, Ethernet copper loop-back cable assembly, a host computer, and an Altera USB-Blaster^TM or ByteBlaster^TM cable assembly
  • Programmable settings include number of packets, packet length, payload data type, and source and destination MAC addresses
  • Step-by-step walk-through instructions, complete design files (including Quartus^® II archive) and Windows XP-based software application for test control and monitoring are provided

Demonstrated Altera Technology

• Stratix II GX FPGAs
• TSE MegaCore function
• Nios^® II embedded processor intellectual property (IP) cores
• Nios II Embedded Design Suite (EDS)
• SOPC Builder
• Avalon^® system interconnect fabric

Figure 1.  Triple-Speed Ethernet Data Path Reference Design

Related Links

• Stratix II GX FPGAs
• Altera Gigabit Ethernet Solutions
• Altera Triple-Speed MegaCore Function
• Altera Nios II MegaCore Function
• Altera Nios II EDS
• Altera SOPC Builder
• PCI Express Development Kit, Stratix II GX Edition
• AN483: Triple-Speed Ethernet Data Path Reference Design (PDF)
• AN440: Accelerating Nios II Networking Applications (PDF)

Reference Designs Disclaimer

These reference design illustrations may be used within Altera Corporation devices only and remain the copyrighted property of Altera. They are being provided on an "as-is" basis and as an accommodation, and therefore all warranties, representations, or guarantees of any kind (whether express, implied or statutory) including, without limitation, warranties of merchantability, non-infringement, or fitness for a particular purpose, are specifically disclaimed. Altera expressly does not recommend, suggest, or require that these examples be used in combination with any other product not provided by Altera.