Altera's FPGAs and SoCs provide the highest performance memory interfaces in the market with a new innovative hard memory controller that offers both flexibility and ease of use to allow for a faster time to market.
The hard memory controller consists of three functions, the UniPHY, the control logic, and the multi-port front end (MPFE). The UniPHY controls the interaction with the I/Os. Its primary function is to handle the timing between the hard memory controller and the external memory. The UniPHY incorporates a programmable delay-locked loop (DLL), which is used to center the eye on the memory bus. This can be done automatically using a Nios® II processor to calibrate the bus and adjust for skew in the line. The MPFE allows up to six processes to access the same memory. Access is determined via deficit round robin to ensure that no data is lost. The hard memory controller can be bypassed with the core having direct access to the UniPHY.
The MPFE is hardened in Arria V devices, but is implemented as soft logic for the Arria 10 devices for user customization. Figure 1 shows the memory interface layers of the hard memory controller.
Figure 1. Memory Interface Layers
Whether you use the IP Toolbench in Qsys or Quartus® II software, it generates an example design, an example driver, the SDRAM controller, and instantiates a phase-locked loop (PLL). This fully functional design example can be simulated, synthesized, and used in hardware. The example driver is a self-test module that issues read and write commands to the controller, and checks the read data to produce the pass and fail and test complete signals. Also included is an efficiency monitor which can determine the actual bandwidth of the memory bus based on the data patterns being used.
Included in the IP Base Suite—FREE with Quartus II Subscription Edition software.
Features
- Support for industry-standard DDR, DDR2, DDR3, and DDR4 SDRAM devices and modules
- Includes support for registered DIMMs
- Supports efficient bank interleaving
- Look-ahead bank management
- Issues activate and precharge commands early
- Use auto-precharge when possible
- In-order read and write (no re-ordering)
- Bank management architecture, which minimizes latency
- Read and write accesses with auto-precharge
- Automatic cancellation of auto-precharge on page hits
- Issues activate and precharge commands early
- Avalon® Memory-Mapped interface
- Adaptor for native interface
- Avalon slave interface for access to the Control and Status Register (CSR)
- Burst size adaptation for efficient DRAM accesses
- Built-in burst adapter
- Combines short local transactions into memory bursts
- Split long local transactions into memory bursts
- Integrated low-latency quarter-rate, half-rate, and full-rate system interface
- Supports an optional half-system interface speed
- Maintains the controller in the faster clock domain to reduce latency
- Flexible, robust design
- 1, 2, 4, or 8 chip-select signals
- Configurable data width including DQ strobe (DQS) read postamble control logic and optional non-DQS read mode for side banks (Stratix® series FPGAs)
- Automatic or user-controlled refresh
- Data mask signals for partial write operations
- Quick and easy implementation
- IP Toolbench-generated constraint script
- Top-level example design shipped as a deliverable with the intellectual property (IP) MegaCore® function
- IP functional simulation models used in Altera® supported VHDL and Verilog HDL simulators
- Available in clear-text for use with custom controller
- Integrated command and data reordering to allow for improved memory bandwidth efficiency
- Power down and self-refresh support
- Well-documented clear text RTL for ease of use
- Qsys compliant to enable system-level design
Performance
- Up to 800-MHz memory speed at quarter-rate (200-MHz controller clock)
- 5-cycle controller latency
Typical expected performance and utilization figures for this MegaCore function are provided in the External Memory Interface Handbook.
