Arria® II FPGA I/Os support a broad range of external memory interfaces, such as DDR3, DDR2, DDR, SDR SDRAM, and QDR II SRAM as shown in the External Memory Interface Support Center. DDR3, DDR2, DDR, and SDR SDRAM are supported by a new self-calibrating datapath available as the ALTMEMPHY megafunction. This megafunction removes process variation and compensates for voltage and temperature variations to achieve data rates up to 600 megabits per second (Mbps), and also ease timing closure.
Table 1 lists resources and technical collateral for building external memory interfaces on Arria II FPGAs.
|Table 1. Arria II FPGA External Memory Resources|
|External Memory Handbook||External memory interfaces including DDR, DDR2, DDR3, QDR II/+, and RLDRAM II provide caching or data storage space in the majority of end systems featuring FPGAs.|
|IP MegaStoreTM Web Page||The web page links to different intellectual property (IP) cores provided by Altera and our partners. The web page also allows you to search for an IP core of your interest.|
|External Memory Design Examples||The page contains design examples for developing external memory solutions on Altera® products.|
|HSPICE Models||Web page providing board design-related resources for Altera devices.|
|IBIS Models||Web page listing of all the IBIS models for Altera devices.|
|Debug GUI User Guide||User guide for the debug GUI.|
|Debug GUI||A .zip file that contains the debug GUI.|
|External Memory Interfaces in Arria GX Devices (PDF)||Describes device internals such as DDR memory interface pins, DQS phase-shift circuitry, and DDR registers.|
|TimeQuest Resources||Provides links and resources to learn more about the TimeQuest timing analyzer.|
|Board Design Guidelines Solution Center||Web page providing board design-related resources for Altera devices.|