The Arria® 10 family offers the largest variety of memories to support your system requirements including DDR4, Hybrid Memory Cube, QDR IV, LPDDR3, and RLDRAM3. The hardened logic interface controller provides higher performance, lower latency, and higher efficiency transactions compared to previous devices. Additions for Arria 10 FPGAs and SoCs include widened bus operation for DDR4 SDRAM (up to 144 pins), burst rate enhancements for QDR IV and RLDRAM 3, and intelligent calibration and skew control via a hardened, memory-controller-dedicated Nios® II embedded processor.
For information about the external memory interface protocols supported by Arria 10, visit the External Memory Interface Support Center.
Table 1 lists resources and technical collateral for building external memory interfaces on Arria 10 FPGAs and SoCs. Note that not all documents and GUIs have complete updates for Arria 10 FPGAs and SoCs.
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Table 1. Arria 10 FPGA and Soc External Memory Resources |
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| Collateral | Description | |
|---|---|---|
| External Memory Interface Handbook (PDF) | This handbook describes the external memory interfaces including DDR2 SDRAM, DDR3 SDRAM, DDR4 SDRAM, LPDDR3, QDR II/QDR II+/QDR IV, and RLDRAM 3 that provide caching or data storage space in the majority of end systems featuring FPGAs and SoCs. | |
| Debugging Memory IP chapter of the External Memory Interface Handbook (PDF) | This chapter in the External Memory Interface Handbook describes how to debug memory intellectual property (IP). | |
| IP MegaStoreTM | This web page links to different IP cores provided by Altera and our partners. The web page also allows you to search for an IP core of your interest. | |
| External memory design examples | This page contains design examples for developing external memory solutions on Altera® products. | |
| HSPICE models | This page provides board design-related resources for Altera devices. | |
| IBIS models | This page lists all the IBIS models for Altera devices. | |
| Debug GUI file | This is a .zip file that contains the debug GUI. | |
| TimeQuest Timing Analyzer Resource Center | This page provides links and resources to learn more about the TimeQuest timing analyzer. | |
| Board Design Guidelines Solution Center | This page provides board design-related resources for Altera devices. | |
