Cyclone® IV FPGAs support a broad range of external memory interfaces, including SDR SDRAM, DDR SDRAM, DDR2 SDRAM, Mobile DDR SDRAM, and QDR II SRAM. Each of the memory standards listed in the External Memory Interface Support Center is supported by a self-calibrating datapath function available as a megafunction. This function removes process variation and compensates for voltage and temperature variations to achieve data rates up to 400 megabits per second (Mbps) and also ease timing closure.
Table 1 lists reference resources for additional information on Cyclone IV FPGA external memory resources.
| Table 1. Cyclone IV FPGA External Memory Resources | ||
| Collateral | Description | |
|---|---|---|
| External Memory Handbook | External memory interfaces including DDR, DDR2, DDR3, QDR II/+, and RLDRAM II provide caching or data storage space in the majority of end systems featuring FPGAs. | |
| IP MegaStoreTM Web Page | This web page links to different intellectual property (IP) cores provided by Altera and our partners. The web page also allows you to search for an IP core of your interest. | |
| External Memory Design Examples | This page contains design examples for developing external memory solutions on Altera products. | |
| HSPICE Models | Web page providing board design-related resources for Altera® devices. | |
| IBIS Models | Web page listing of all the IBIS models for Altera devices. | |
| Debug GUI User Guide (PDF) | User guide for the debug GUI. | |
| Debug GUI | A .zip file that contains the debug GUI. | |
| TimeQuest Resources | Provides links and resources to learn more about the TimeQuest timing analyzer. | |
| Board Design Guidelines Solution Center | Web page providing board design-related resources for Altera devices. | |
