Cyclone® III FPGAs support a broad range of external memory interfaces, such as SDR SDRAM, DDR SDRAM, DDR2 SDRAM, and QDR II SRAM. Each of the memory standards as shown in the External Memory Interface Support Center is supported by a new self-calibrating datapath available as a megafunction (ALTMEMPHY) that removes process variation and compensates for voltage and temperature variations to achieve data rates up to 400 megabits per second (Mbps) and ease timing closure.
Table 1 lists reference resources for additional information on Cyclone III FPGA external memory.
| Table 1. Cyclone III FPGA External Memory Resources | ||
| Collateral |
Description |
|
|---|---|---|
| Start Here | ||
| Interfacing DDR & DDR2 SDRAM with Cyclone III FPGAs (PDF) | Describes the interface architecture, signals, and timing analysis for a DDR/DDR2 SDRAM memory. | |
| Device Selection | ||
| Selecting the Right High-Speed Memory Technology for Your System (PDF) | Describes how to select the right memory for your application. | |
| External Memory Interfaces (PDF) | Describes Cyclone III FPGA internals such as DDR memory interface pins, DQS phase-shift circuitry, and DDR registers. | |
| Intellectual Property (IP) and Megafunction User Guides | ||
| ALTMEMPHY Megafunction User Guide (PDF) | Describes the ALTMEMPHY megafunction functionality and how to interface with Altera's DDR and DDR2 SDRAM high-performance controllers and third-party controllers. | |
| DDR/DDR2 SDRAM Controller Compiler User Guide (PDF) | Describes the controller interface and also the design flow using SOPC Builder and MegaWizardTM Plug-In Manager. | |
| IP MegaStoreTM | The web page links to different IP cores provided by Altera and partners. The web page also allows you to search for IP. | |
| Timing Analysis | ||
| TimeQuest Timing Analyzer (PDF) | Learn about the features of the TimeQuest timing analyzer and how to constrain your design with Synopsys Design Constraints (SDC) commands. | |
| Constraining and Analyzing Timing for External Memory Interfaces in Stratix III and Cyclone III FPGAs (PDF) | Learn how to quickly meet timing with your external memory interfaces. | |
| TimeQuest Resources | This page provides links to resources for you to learn more about the TimeQuest timing analyzer. | |
| Multi-CS Calculator | This calculator is a Microsoft Excel spreadsheet used to manually de-rate timing for Stratix® III and Cyclone III multi-rank external memory interface designs. | |
| Models and Board Design Guidelines | ||
| Board Design Guidelines Solution Center | The web page provides you with board design-related resources for Altera® devices. Its goal is to help you implement successful high-speed PCBs that integrate Altera device(s) and other elements. | |
| HSPICE Models | A web page listing of all the HSPICE models for Altera devices. | |
| IBIS Models | A web page listing of all the IBIS models for Altera devices. | |
| Kits and Boards | ||
| Cyclone III FPGA Starter Kit | The economical Cyclone III FPGA Starter Kit is an easy-to-use, comprehensive development kit. | |
