The Stratix® V FPGA I/O structure is based on the successful Stratix III and Stratix IV FPGA I/O structure with enhancements to achieve unprecedented performance. The I/O structure itself is ideal for interfacing to existing and emerging external memory standards.
For information about the external memory interface protocols supported by Stratix V, visit the External Memory Interface Support Center.
Table 1 lists resources and technical collateral for building external memory interfaces on Stratix V FPGAs.
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Table 1. Stratix V FPGA External Memory Resources |
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| Collateral | Description | |
|---|---|---|
| External Memory Handbook | External memory interfaces including DDR, DDR2, DDR3, QDR II/QDR II+, and RLDRAM II provide caching or data storage space in the majority of end systems featuring FPGAs. | |
| IP MegaStoreTM Web Page | This web page links to different intellectual property (IP) cores provided by Altera and our partners. The web page also allows you to search for an IP core of your interest. | |
| External Memory Design Examples | This page contains design examples for developing external memory solutions on Altera® products. | |
| HSPICE Models | Web page providing board design-related resources for Altera devices. | |
| IBIS Models | Web page listing of all the IBIS models for Altera devices. | |
| Debug GUI User Guide (PDF) | User guide for the debug GUI. | |
| Debug GUI | A .zip file that contains the debug GUI. | |
| TimeQuest Resources | Provides links and resources to learn more about the TimeQuest timing analyzer. | |
| Board Design Guidelines Solution Center | Web page providing board design-related resources for Altera devices. | |
