Stratix® II and Stratix II GX devices support a broad range of external memory interfaces (refer to External Memory Interface Support Center).
Table 1 lists resources and technical collateral for building an external memory interface using Stratix II and Stratix II GX devices.
| Table 1. Stratix II and Stratix II GX External Memory Interface Resources | ||
| Collateral | Description | Key (1) |
|---|---|---|
| Start Here | ||
| AN 449: Design Guidelines for Implementing External Memory Interfaces in Stratix II & Stratix II GX Devices (PDF) | Describes typical memory interface design flow for Stratix II and Stratix II GX devices. Also provides links to pertinent literature for each design step. | A |
| Interfacing DDR Memory with Stratix II Devices | ||
| AN 328: Interfacing DDR2 SDRAM with Stratix II Devices (PDF) | Describes the interface architecture, signals, and timing analysis for a DDR2 SDRAM memory. | L |
| AN 327: Interfacing DDR SDRAM with Stratix II Devices (PDF) | Describes the interface architecture, signals, and timing analysis for a DDR SDRAM memory. | L |
| AN 326: Interfacing QDR II & QDR II+ SRAM with Stratix II, Stratix, and Stratix GX Devices (PDF) | Describes the interface architecture, signals, and timing analysis for QDR II and QDR II+ SRAM memory. | L |
| AN 325: Interfacing RLDRAM II with Stratix II, Stratix, & Stratix GX Devices (PDF) | Describes the interface architecture, signals, and timing analysis for an RLDRAM II memory. | L |
| Device Selection | ||
| Selecting the Right High-Speed Memory Technology for Your System (PDF) | Describes how to select the right memory for your application. | A/L |
| The Efficiency of the DDR & DDR2 SDRAM Controller Compiler (PDF) | Describes terminologies such as bandwidth, efficiency, and read latency. | A/L |
| External Memory Interfaces in Stratix II and Stratix II GX Devices (PDF) | Describes Stratix II and Stratix II GX device internals such as DDR memory interface pins, DQS phase-shift circuitry, and DDR registers. | A/L |
| IP/Megafunction User Guides | ||
| DDR/DDR2 SDRAM High-Performance Controller User Guide (PDF) | Describes the controller interface and the design flow using the MegaWizardTM Plug-In Manager and ALTMEMPHY. | A |
| DDR/DDR2 SDRAM Controller Compiler User Guide (PDF) | Describes the controller interface and the design flow using SOPC Builder and the MegaWizard Plug-In Manager. | L |
| ALTMEMPHY Megafunction User Guide (PDF) | Describes the ALTMEMPHY megafunction functionality and how to interface with Altera's DDR/DDR2 SDRAM high-performance controllers and third-party controllers. | A |
| IP MegaStoreTM | Links to different intellectual property (IP) cores provided by Altera and their partners. The web page also allows you to search for an IP of your interest. | A/L |
| Applications and Debug | ||
| AN 398: Using DDR/DDR2 SDRAM with SOPC Builder (PDF) | Describes the design flow for instantiating a DDR2 controller in SOPC Builder and using the SignalTapTM II logic analyzer for verification of the read and write transactions. | L |
| AN 392: Implementing Multiple Legacy DDR/DDR2 SDRAM Controller Interfaces (PDF) | Describes the steps for designing multiple legacy DDR2 controllers into a single FPGA. | L |
|
AN 462: Implementing Multiple Memory Interfaces Using the ALTMEMPHY Megafunction (PDF) Example Design for AN 462: top.qar |
Describes the design methodology for implementing multiple controllers in a single FPGA using ALTMEMPHY. | A |
|
AN 415: DDR & DDR2 SDRAM ECC Reference Design (PDF) ECC Reference Design Files |
Describes how to use the error correction coding (ECC) design block with DDR and DDR2 SDRAM controllers. | L |
| AN 380: Test DDR or DDR2 SDRAM Interfaces on Hardware Using the Example Driver (PDF) | Describes the verification of an example design using functional and hardware simulation. | L |
| Timing Analysis | ||
|
DDR Timing Wizard User Guide (PDF) |
Describes the timing analysis methodology using the DDR timing wizard (DTW) and describes how to close timing using the dtw_timing_analysis.tcl Tcl script. | L |
| TimeQuest Timing Analyzer (PDF) | Learn about the features of the TimeQuest analyzer and how to constrain your design with Synopsys Design Constraints (SDC) commands. | A/L |
| TimeQuest Resources | Provides links and resources to learn more about the TimeQuest analyzer. | A/L |
| Models and Board Design Guidelines | ||
| AN 444: Dual DIMM DDR2 SDRAM Memory Interface Design Guidelines (PDF) | Describes the design guidelines for developing a dual DIMM DDR2 SDRAM memory interface. | A |
| AN 408: DDR2 Memory Interface Termination, Drive Strength and Loading Design Guidelines (PDF) | Describes design guidelines for termination, drive strength, and loading. | A/L |
| Board Design Guidelines Solution Center | Web page providing board design-related resources for Altera® devices. | A/L |
| HSPICE Models | Web page listing of all the HSPICE models for Altera devices. | A/L |
| IBIS Models | Web page listing of all the IBIS models for Altera devices. | A/L |
| System Validation Reports | ||
| Stratix II DDR2 System Validation Summary (PDF) | Describes the results of system validation, which consists of a series of comprehensive tests for robust functionality under challenging environments. | L |
| Kits and Boards | ||
| PCI Express® Development Kit, Stratix II GX Edition | Delivers a complete PCI Express-based development platform. Includes DDR2 SDRAM memory on the board. | A/L |
| Audio Video Development Kit, Stratix II GX Edition | Provides a complete video and image processing development platform. Includes DDR2 SDRAM memory. | A/L |
| Nios® II Development Kit, Stratix II Edition | Altera's Nios II Development Kit, Stratix II Edition provides a complete development environment, including everything hardware and software designers need for system-level designs and for testing the external memory interface. | L |
- L = Legacy integrated static datapath and controller (DDR and DDR2 SDRAM, RLDRAM II, and QDR II SRAM controller MegaCore® functions)
- A = New auto-PHY solution delivered via the ALTMEMPHY megafunction
