The Stratix® III I/O structure has been completely redesigned from the ground up to provide flexible and high-performance support for existing and emerging external memory standards (refer to External Memory Interface Support Center).
| Table 1. Stratix III External Memory Resources | ||
| Collateral | Description | Key (1) |
|---|---|---|
| Start Here | ||
| AN 435: Design Guidelines for Implementing DDR & DDR2 SDRAM Interfaces in Stratix III Devices (PDF) | Describes typical DDR and DDR2 SDRAM memory interface design flow for Stratix III devices. Also provides links to pertinent literature for each design step. | A |
| AN 436: Design Guidelines for Implementing DDR3 SDRAM Interfaces in Stratix III Devices (PDF) | Describes typical DDR3 SDRAM memory interface design flow for Stratix III devices. Also provides links to pertinent literature for each design step. | A |
| Device Selection | ||
| Selecting the Right High-Speed Memory Technology for Your System (PDF) | Describes how to select the right memory for your application. | A/L |
| The Efficiency of the DDR & DDR2 SDRAM Controller Compiler (PDF) | Describes terminologies such as bandwidth, efficiency, and read latency. | A/L |
| External Memory Interfaces in Stratix III Devices (PDF) | Describes Stratix III device internals such as DDR memory interface pins, DQ strobe (DQS) phase-shift circuitry, and DDR registers. | A |
| Intellectual Property (IP) and Megafunction User Guides | ||
| DDR/DDR2 SDRAM High-Performance Controller User Guide (PDF) | Describes the controller interface and the design flow using the MegaWizardTM Plug-In Manager and ALTMEMPHY megafunction. | A |
| ALTMEMPHY Megafunction User Guide (PDF) | Describes the ALTMEMPHY megafunction functionality and how to interface with Altera’s DDR and DDR2 SDRAM high-performance controllers and third-party controllers. | A |
| IP MegaStoreTM | The web page links to different IP cores provided by Altera and our partners. The web page also allows you to search for IP cores. | A/L |
| Timing Analysis | ||
| AN 438: Constraining & Analyzing Timing for External Memory Interfaces in Stratix III Devices (PDF) | Describes the various timing-related paths, constraints, and analysis used by the ALTMEMPHY megafunction in Stratix III designs. | A |
| TimeQuest Timing Analyzer (PDF) | Learn about the features of the TimeQuest timing analyzer and how to constrain your design with Synopsys Design Constraints (SDC) commands. | A/L |
| TimeQuest Resources | Provides links and resources to learn more about the TimeQuest timing analyzer. | A/L |
| Multi-CS Calculator | This calculator is a Microsoft Excel spreadsheet used to manually de-rate timing for Stratix III and Cyclone® III multi-rank external memory interface designs. | A |
| Models and Board Design Guidelines | ||
| AN 444: Dual DIMM DDR2 SDRAM Memory Interface Design Guidelines (PDF) | Describes the design guidelines for developing a dual DIMM DDR2 SDRAM memory interface. | A/L |
| Board Design Guidelines Solution Center | Web page providing board design-related resources for Altera® devices. | A/L |
| HSPICE Models | Web page listing of all the HSPICE models for Altera devices. | A/L |
| IBIS Models | Web page listing of all the IBIS models for Altera devices. | A/L |
- L = Legacy core. DDR and DDR2 SDRAM Controller MegaCore® function
(integrated static datapath and controller solution) - A = New auto-PHY solution delivered via the ALTMEMPHY megafunction
