External Memory Solutions Center: DDR2 SDRAM

Altera offers a complete PHY and controller solution for building a DDR2 SDRAM interface in Altera^® FPGAs and HardCopy^® ASICs. The PHY megafunctions (ALTMEMPHY and UniPHY) and the associated High-Performance Memory Controller II (HPMCII) are two distinct products. The DDR2 SDRAM PHY and controller are MegaCore^® functions and you can use them separately or together. The rationale behind splitting the PHY interface and controller is to allow you to design specialized controllers, while still benefiting from the Altera PHY. When combined, they create a complete integrated memory interface solution. The External Memory Interface Support Center shows the DDR2 SDRAM performance of Altera FPGAs and HardCopy ASICs.

About the DDR2 SDRAM Solution (PHY Megafunctions and Controller)

The Altera DDR2 SDRAM HPMCII MegaCore function provides a simplified interface to industry-standard DDR2 SDRAM. The PHY megafunctions (ALTMEMPHY and UniPHY) are an interface between a memory controller and the memory devices, and perform read and write operations to the memory. The HPMCII MegaCore function works in conjunction with the PHYs to create a complete controller and PHY solution for DDR2 SDRAM.

The DDR2 SDRAM HPMCII MegaCore function and PHY megafunctions offer full-rate or half-rate DDR2 SDRAM operation. The HPMCII MegaCore function offers high performance and efficiency along with new advanced features, such as advanced bank management with command look-a-head. The PHY megafunctions (ALTMEMPHY and UniPHY) support the PHY requirements to interface to DDR2 SDRAM devices. UniPHY is available for Stratix^® and Arria^® GX device families.

Selecting the Appropriate Core

For more information on using the ALTMEMPHY, UniPHY, and HPMCII functions, see the External Memory Interfaces Handbook.

External Memory Solutions Center: DDR2 SDRAM

About the DDR2 SDRAM Solution (PHY Megafunctions and Controller)

Selecting the Appropriate Core

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