Memory Solutions Center: DDR3 SDRAM

Altera offers a complete PHY and controller solution for building a DDR3 SDRAM interface in Altera^® FPGAs and HardCopy^® ASICs. The PHY megafunctions (ALTMEMPHY and UniPHY) and associated High-Performance Memory Controller II (HPMCII) are two distinct product types. The DDR3 SDRAM PHY and controller are MegaCore^® functions and can be used separately or together. The rationale behind splitting the PHY interface and controller is to allow you to design specialized controllers, while still benefiting from the Altera PHY. When combined, they create a complete integrated memory interface solution. The External Memory Interface Support Center shows the DDR3 SDRAM performance of Altera FPGAs and HardCopy ASICs.

About the DDR3 SDRAM Solution (PHY and Controller)

The Altera DDR3 SDRAM HPMCII MegaCore function provides a simplified interface to industry-standard DDR3 SDRAM. The PHY megafunctions (ALTMEMPHY and UniPHY) are an interface between a memory controller and the memory devices, and perform read and write operations to the memory. The MegaCore controller function works in conjunction with the PHY megafunctions to create a complete controller and PHY solution for DDR3 SDRAM.

The DDR3 SDRAM HPMCII MegaCore function and PHY megafunctions offer a full-rate or half-rate DDR3 SDRAM interface. The HPMCII MegaCore function offers high performance and efficiency along with advanced features, such as advanced bank management with command look-ahead. The PHY megafunctions (ALTMEMPHY and UniPHY) support the PHY requirements to interface with DDR3 SDRAM devices. UniPHY is available for the Stratix^® and Arria^® GX device families.

Selecting the Appropriate Core

For more information on the use of the ALTMEMPHY and UniPHY megafunctions and the HPMCII MegaCore function, see the External Memory Interfaces Handbook

Memory Solutions Center: DDR3 SDRAM

About the DDR3 SDRAM Solution (PHY and Controller)

Selecting the Appropriate Core

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