Altera offers a complete Physical Interface (PHY) and memory controller solution for building a DDR4 SDRAM interface in Altera® Stratix® 10 and Arria® 10 FPGAs and SoCs. The PHY megafunctions and associated High-Performance Memory Controller II (HPMCII) are two distinct product types. The DDR4 SDRAM PHY and controller MegaCore® functions can be used separately or together. The ability to seperate the PHY interface from the controller allows a user to design a custom memory controller, while still benefiting from the Altera PHY. When combined, they create a complete integrated memory interface solution.
About the DDR4 SDRAM Solution (PHY and Controller)
The Altera DDR4 SDRAM HPMCII MegaCore function provides a simplified interface to the industry-standard DDR4 SDRAM. The PHY megafunctions are the interface between the memory controller and the external memory devices, and perform read and write operations to the memory. The MegaCore controller function works in conjunction with the PHY megafunctions to create a complete controller and PHY solution for DDR4 SDRAM.
- External Memory Interface Spec Estimator
- Debug GUI User Guide (PDF)
- Debug GUI Software (ZIP)