Altera provides complete system solutions to help memory designers successfully interface Altera® FPGAs and SoCs with a variety of DRAM devices.
DRAM devices are volatile memories offering a lower cost per bit than SRAM devices. A compact memory cell consisting of a capacitor and a transistor makes this possible over the six-transistor cell used in SRAM. However, the capacitor will invariably discharge over time, thus causing the memory cell to lose its state, which means that DRAM memory needs to be refreshed periodically. Generally, you would choose SRAM devices for applications where latency or low interface complexity is important and you would choose DRAM where cost per bit is important. Special types of DRAM challenge this norm by offering improved random access latency, as well as a lower cost per bit.
DDR4 SDRAM
DDR4 SDRAM is the next generation high speed SDRAM interface standard. The primary benefit of DDR4 SDRAM is a higher range of clock frequencies and data transfer rates, thus enabling higher bus rates and higher peak rates than earlier memory technologies. In addition, the DDR4 SDRAM standard uses lower standard voltages and follows a point-to-point data topology where each memory controller is connected to a single DIMM. The advantages of DDR4 SDRAM architecture over DDR3 SDRAM architecture are summarized as follows:
- Data rate speed ranges from 1,600 to 3,200 Mbps
- Device capacity ranges from 8 Gb to 32 Gb (or larger)
- Power is lower than DDR3 SDRAM due to reduced I/O and core voltages
DDR3 SDRAM
DDR3 SDRAM is an improvement over its predecessor, DDR2 SDRAM. The primary benefit of DDR3 SDRAM is the ability to transfer at twice the data rate of DDR2 SDRAM, thus enabling higher bus rates and higher peak rates than earlier memory technologies. In addition, the DDR3 SDRAM standard allows for greater chip capacities. The advantages of DDR3 SDRAM architecture over DDR2 SDRAM architecture are summarized as follows:
- Data rate speed ranges from 800 to 1,600 Mbps
- Device capacity ranges from 512 Mb to 8 Gb
- Power is lower than DDR2 SDRAM due to reduced I/O and core voltage
DDR2 SDRAM
DDR2 SDRAM is an evolution of DDR SDRAM. It operates using a lower voltage (1.8 V). DDR2 SDRAM offers increased densities and even higher performance through higher bus speeds and an optimized interface. The advantages of DDR2 SDRAM architecture over DDR SDRAM architecture are summarized as follows:
- Data rate speed ranges from 400 to 667 Mbps
- Power is lower than DDR SDRAM due to reduced I/O and core voltage
- Smaller footprint for FBGA packages
DDR SDRAM
Double data rate (DDR) SDRAM is an evolution of single data rate (SDR) SDRAM. It offers higher performance through increased bus speeds using a lower I/O voltage (2.5 V), and most importantly, data transfer on both clock edges, doubling the raw bandwidth. DDR SDRAM is a widely established memory technology. It offers the lowest cost per bit, due in part to its broad acceptance in almost any marketplace.
RLDRAM 2
RLDRAM 2 is the second generation of RLDRAM. It is a development of DDR SDRAM, designed to address the low latency requirements of certain applications, such as packet buffers in high-performance line cards. RLDRAM 2 has a high-performance DDR data bus and offers a non-multiplexed address bus, reducing the number of clock cycles to initiate read or write applications. A banked architecture also reduces access time. In some systems, RLDRAM 2 eliminates the need for specialized content-addressable memory (CAM) or SRAM.
RLDRAM 3
RLDRAM 3 is the third generation of RLDRAM. It is a development of DDR SDRAM, designed to address the low latency requirements of certain applications, such as packet buffers in high-performance line cards. RLDRAM 3 has a high-performance DDR data bus and offers a non-multiplexed address bus, reducing the number of clock cycles to initiate read or write applications. A banked architecture also reduces access time. In some systems, RLDRAM 3 eliminates the need for specialized CAM or SRAM.
SDR SDRAM
SDR SDRAM is the first generation of synchronous DRAM. It improves memory bandwidth over extended data out (EDO) DRAM by offering data transfer up to once-per-clock cycle.
DRAM Memory Vendors
Related Links
- External Memory Interface Spec Estimator
- Memory Solution Center
- Memory Interface Design Online Demonstration
- Memory Controller IP MegaStoreTM
- Device Support Center (Signaling and Board Design)