Driven predominantly by the needs of networking applications, a new type of DRAM optimized for low-latency access, RLDRAM, was developed. Most DRAM memory types need both a row and column phase on a multiplexed address bus to support full random access. RLDRAM supports a non-multiplexed address, saving bus cycles.
The multi-bank architecture in RLDRAM devices allows pipelined accesses. This means the row- and column-line lengths are smaller than in DRAM devices, reducing capacitance and improving access time. RLDRAM utilizes higher operating frequencies and uses the 1.8-V, high-speed transistor logic (HSTL) standard with DDR data transfer to provide a very high throughput.
RLDRAM II offers faster random access times, on-die termination, a delay-locked loop (DLL) for higher frequency operation, larger densities, wider data paths, and higher bus utilization compared with RLDRAM.
Altera offers complete system solutions, including technical collateral, software support, intellectual property (IP) cores (RLDRAM II Controller MegaCore® function), demo boards, and simulation models to help you successfully interface Altera® FPGAs and HardCopy® ASICs with RLDRAM II memories. Table 1 lists RLDRAM II memory interface performance support in Altera devices. The detailed performance specification can be found using the External Memory Interface Spec Estimator.
|Table 1. Altera FPGA and HardCopy ASIC RLDRAM II Memory Interface Performance Support|
|Device||RLDRAM II Interface Performance|
|Stratix® V||1066 Mbps common I/O (CIO) (533 MHz)|
|Stratix IV||1066 Mbps CIO (533 MHz)|
|Stratix III||800 Mbps CIO (400 MHz)|
|Stratix II GX||600 Mbps CIO (300 MHz)|
|Stratix II||600 Mbps CIO (300 MHz)|
|Stratix GX||400 Mbps (200 MHz)|
|Stratix||400 Mbps (200 MHz)|
|HardCopy IV||700 Mbps CIO (350 MHz)|
|HardCopy III||700 Mbps CIO (350 MHz)|
|HardCopy II||500 Mbps CIO (250 MHz)|
|Arria® V||800 Mbps CIO (400 MHz)|
|Arria II GZ||700 Mbps CIO (350 MHz)|
Altera offers technical collateral (shown in Table 2) that contains information on device support for RLDRAM II.
|Table 2. RLDRAM II Technical Documentation|
Stratix V Device Handbook:
External Memory Interfaces in Stratix V Devices (PDF) chapter
Stratix IV Device Handbook:
External Memory Interfaces in Stratix IV Devices (PDF) chapter
|Stratix III Device Handbook:
External Memory Interfaces in Stratix III Devices (PDF) chapter
|Arria V Device Handbook:
External Memory Interfaces in Arria V Devices (PDF) chapter
|Selecting the Right High-Speed Memory Technology for Your System (PDF)||All|
|RLDRAM II Controller MegaCore Function User Guide (PDF)||HardCopy II
Stratix II GX
|Hardware Test Results||Applicable
|Hardware Test Results||Stratix|
Software Support and Tools
Altera offers software (shown in Table 3) that aids in the RLDRAM II memory interface design process.
|Table 3. RLDRAM II Software Support and Tools|
|TimeQuest Timing Analyzer||All devices|
|IBIS Models for I/O Buffers||Stratix
This RLDRAM II reference design meets timing at 400 MHz, works on multiple Stratix III FPGA memory boards, and simulates properly in ModelSim® 6.1g SE. The design is in half-rate mode with a QDR-like ALTMEMPHY calibration, including power-up calibrated, dynamic on-chip termination (OCT) support for the DQ pins. For details on the RLDRAM II reference design, contact Altera or your local Altera FAE.
If you target the Micron MT49H16M36HT-18 device with burst length of 4 and configuration of 3, you can use this design as is. Otherwise, you can use this design as a reference to create your own variation of an RLDRAM II controller/PHY. The design is in clear-text HDL, so you can see what each module does by looking at the RTL Viewer or performing simulation in ModelSim.
Development Kits and Hardware Reference Platforms
Memory hardware reference platforms available from Altera are listed in Table 4. The Gerber files, layout, termination recommendations, and signal integrity analysis information of these reference platforms are also available.
|Table 4. RLDRAM II Development Kits and Hardware Reference Platforms|
|Board Name||Vendor||Contact Information|
|Stratix FPGA Memory Reference Platform for DDR SDRAM and RLDRAM II||Altera||Contact Altera or local Altera FAE|
RDLRAM and RLDRAM II Memory Vendors
- Micron, Inc.
- Renesas, Inc. (Under the LLDRAM Label: Known Differences PLL lock time of 15us)
- GSI Technology, Inc. (Under the LLDRAM Label)
- External Memory Interface Spec Estimator
- External memory interfaces documentation
- Altera's Signal Integrity Center
- Altera's External Memory Interface Solutions Center
- Memory interface design online demonstration
- Micron RLDRAM home page
- External Memory Device Interfaces in Stratix II, Stratix, and Stratix GX FPGAs
- RLDRAM II Controller MegaCore Function
- Memory Controller IP MegaStoreTM
- Device support center (Signaling and board design)