The Hybrid Memory Cube (HMC) is a revolutionary, next generation DRAM technology that promises to address some of the major challenges faced by system designers. The Hybrid Memory Cube combines the best of logic and DRAM processes into a single heterogeneous package using 3D Through Silicon Via (TSV) technology to stack multiple DRAM layers over a base logic layer. The DRAM layers handle data only, while the logic layer handles all control within the HMC. The Hybrid Memory Cube technology specification has been developed by the Hybrid Memory Cube Consortium (HMCC). Altera is one of the leading consortium members and has been collaborating with Micron Technology in defining the HMC interface specification and carrying out system-level interoperability testing. The HMC specification was ratified by the consortium in April 2013.
The Hybrid Memory Cube uses a transceiver-based interface which supports up to four serial links. Each link is built using 16 full duplex transceiver channels, resulting in up to a total of 64 channels for the interface. Each link can run at data rates ranging from 10, 12.5, 15 Gbps providing up to 1 Tbps of raw aggregated interface bandwidth in each direction.
Generation 10 FPGA/SoC + HMC: Solution for Next Generation Systems
The Hybrid Memory Cube technology, coupled with Altera’s Generation 10 FPGAs and SoCs, provides maximum bandwidth, lower power and board area efficiency making it an ideal solution for next generation high performance computing, military and wireline communication applications. The Generation 10 devices include Arria® 10 and Stratix® 10 FPGAs and SoCs.
Altera offers Stratix 10 and Arria 10 FPGAs and SoCs with high speed serial transceivers and the intellectual property required to interface to the Hybrid Memory Cube. Arria 10 FPGAs and SoCs will be the first devices from the Generation 10 portfolio to support the Hybrid Memory Cube technology in volume production.
- Up to 96 transceiver channels
- 28 Gbps low power and 17 Gbps backplane capable transceivers
- Up to 144 transceiver channels
- 56 Gbps trancievers and 28Gbps backplane capable transceivers
Altera’s Generation 10 HMC solution promises to deliver significant advantages over solutions using conventional SDRAM technology.
- Arria 10 - 15 percent higher core performance than today’s highest performance Stratix V FPGAs, 40 percent lower power compared to the lowest power Arria V midrange FPGAs.
- Stratix 10 - Operating frequency over one gigahertz and two times the core performance of current high-end 28 nm FPGAs,70 percent lower power at performance levels equivalent to the previous generation.
- HMC - More than 15x the bandwidth of a DDR3 SDRAM module,70 percent less energy per bit than DDR3 SDRAM technologies, Stacked architecture uses nearly 90 percent less physical space than today’s RDIMMs.
Altera FPGA and Micron HMC Inter Op Announcement
Altera has demonstrated successful interoperability between its Stratix V FPGAs and Micron’s Hybrid Memory Cube (HMC) device. The demonstration successfully passes data traffic of varying packet sizes between the Stratix V FPGA and the Hybrid Memory Cube using a full-width 16 transceiver based HMC link. The demonstration is an important milestone in the FPGA industry and provides an early proof point that production support of HMC will be delivered with Altera’s Generation 10 portfolio, in alignment with market timing, and includes both Stratix 10 and Arria 10 FPGAs and SoCs. This technology achievement enables system designers to evaluate the benefits of HMC with FPGAs and SoCs for next-generation communications and high-performance computing designs.
Related Links
- Hybrid Memory Cube Consortium (External Site)
- Arria 10 FPGA and SoC External Memory Interface Resources
