QDR II/QDR II+ SRAM devices enable you to maximize memory bandwidth with separate read and write ports. The QDR II SRAM architecture features two data ports operating twice per clock cycle to deliver a total of four data words per cycle. The resulting performance increase is particularly valuable in bandwidth-intensive applications.
Altera offers a complete PHY and controller solution for building a QDR II/QDR II+ SRAM interface in the Altera® FPGAs and HardCopy® ASICs. The PHY (UniPHY) and associated controller High-Performance Memory Controller II (HPMCII) are two distinct product types. The PHY and controller are MegaCore® functions and you can use them separately or together. The rationale behind splitting the PHY interface and controller is to allow you to design specialized controllers, while still benefiting from the Altera PHY. When combined, they create an integrated PHY and controller solution. The External Memory Interface Support Center shows the QDR II/QDR II+ SRAM memory interface performance of Altera FPGAs and HardCopy ASICs.
Technical Documentation
Altera offers the following technical documentation that contains information on device support for the QDR and QDR II memory interfaces, as shown in Table 1.
| Table 1. QDR II SRAM Technical Documentation | |
| Device Handbooks | Applicable Devices |
|---|---|
| Stratix® V Device Handbook: External Memory Interfaces in Stratix IV Devices (PDF) chapter |
Stratix V |
| Stratix IV Device Handbook: External Memory Interfaces in Stratix IV Devices (PDF) chapter |
Stratix IV HardCopy IV |
|
Stratix III Device Handbook: External Memory Interfaces in Stratix III Devices (PDF) chapter |
Stratix III HardCopy III |
| Stratix II Device Handbook: External Memory Interfaces in Stratix II and Stratix II GX Devices (PDF) chapter and Selectable I/O Standards in Stratix II and Stratix II GX Devices (PDF) chapter |
Stratix II HardCopy II |
| Arria® V Device Handbook: External Memory Interfaces in Arria V Devices (PDF) chapter |
Arria V, Arria V SoC |
|
Arria II GX Device Handbook: External Memory Interfaces in Arria II Devices (PDF) chapter |
Arria II GX |
| White Papers | Applicable Devices |
| Selecting the Right High-Speed Memory Technology for Your System (PDF) | All |
| User Guides | Applicable Devices |
| QDR II SRAM Controller MegaCore Function User Guide (PDF) |
Stratix II/Stratix II GX |
| Hardware Test Results | Applicable Devices |
| Hardware Test Results | Stratix |
Software Support and Tools
Altera offers the tools shown in Table 3 to aid in the QDR II and QDR II+ SRAM memory interface design process.
| Table 3. QDR II SRAM Software and Support Tools | |
| Feature | Applicable Devices |
|---|---|
| TimeQuest Timing Analyzer | All |
| IBIS Models for I/O Buffers | All |
IP Cores and Reference Designs
Table 4 lists QDR II SRAM controller intellectual property (IP) cores and reference designs available from Altera.
| Table 4. QDR II SRAM IP Cores and Reference Designs | |||
| Controller Name | Free Evaluation | Vendor | Devices Supported |
|---|---|---|---|
| QDR II SRAM Controller MegaCore Function | Yes | Altera | Stratix V, Stratix IV, Stratix III, Stratix II, Stratix II GX, Stratix, Stratix GX, HardCopy III, HardCopy II |
Development Kits and Hardware Reference Platforms
Table 5 lists memory hardware reference platforms available from Altera. The Gerber files, layout, termination recommendations, and signal integrity analysis information of these reference platforms are also available.
| Table 5. QDR II SRAM Development Kits and Hardware Reference Platforms | ||
| Board Name | Vendor | Contact Information |
|---|---|---|
| QDR II SRAM Stratix Memory Reference Platform | Altera | Contact Altera or your local Altera FAE |
QDR II SRAM Vendors
Related Links
- External Memory Interface Spec Estimator
- External memory interfaces documentation
- Altera's Signal Integrity Center
- Altera's External Memory Interface Solutions Center
- Memory interface design online demonstration
- Stratix V Device I/O Connectivity
- Stratix IV FPGA I/O Connectivity
- Stratix Series FPGA I/O Connectivity
- External Memory Device Interfaces in Stratix II, Stratix, and Stratix GX FPGAs
- External Memory Device Interfaces in Cyclone® II and Cyclone FPGAs
- External Memory Interfaces in Cyclone IV Devices (PDF)
