Zero-bus turnaround (ZBT) SRAM with no bus latency (NoBL) memory is a synchronous-burst SRAM with a simplified interface that fully uses available bandwidth. ZBT SRAM devices use the full bandwidth because they do not require turnaround cycles (that is idle cycles between read and write operations). In contrast, standard-synchronous burst SRAMs require turnaround cycles which significantly reduce the available bandwidth.
Altera® FPGAs support high-performance ZBT SRAM interfaces as shown in Table 1.
|Table 1. ZBT SRAM Memory Interface Performance Support in Altera FPGAs|
|Device||Maximum ZBT SRAM Interface Performance|
|Stratix®||200 Mbps (200 MHz)|
|Stratix GX||200 Mbps (200 MHz)|
|APEX™ II||200 Mbps (200 MHz)|
Altera offers technical collateral that contains information on device support for ZBT SRAM interfaces as shown in Table 2.
|Table 2. ZBT SRAM Technical Documentation|
|Device Handbooks||Applicable Device(s)|
|Stratix / Stratix GX Device Handbook:
External Memory Device Interfaces (PDF) chapter
Using Selectable I/O Standards (PDF) chapter
|Stratix / Stratix GX|
|White Papers||Applicable Device(s)|
|Selecting the Right High-Speed Memory Technology for Your System (PDF)||All|
|Application Notes||Applicable Device(s)|
|AN 329: ZBT SRAM Controller Reference Design (PDF)||Stratix / Stratix GX|
Software Support & Tools
Altera offers the tools that aid in the ZBT SRAM memory interface design process as shown in Table 3.
|Table 3. ZBT SRAM Software Support & Tools|
|IBIS Models for I/O Buffers||Stratix
List of ZBT SRAM Vendors
- External Memory Device Interfaces in Stratix II / Stratix / Stratix GX Devices
- External Memory Device Interfaces in CycloneTM II / Cyclone Devices
- External Memory Device Interfaces in APEX II Devices