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An efficient strategy for determining the PCB decoupling scheme is to use the Frequency Domain Target Impedance Method (FDTIM). This method is used by the Altera PDN Decoupling Calculator Tool and is the recommended method for determining the board-level decoupling requirements using Altera FPGAs.

For more information on FDTIM method, refer to Comparison of Power Distribution Network Design Methods (PDF) presented at the DesignCon 2006 TecForum TF-MP3.

FDTIM Decoupling Concepts

The key concept of the FDTIM method is the determination of the target impedance (Z_TARGET) for the power rail under consideration. A reliable decoupling strategy warrants for the effective power rail impedance (Z_EFF) to be lower than the Z_TARGET from a few KHz up to the highest frequency of interest (f_TARGET). Figure 1 illustrates this concept, where the solid horizontal blue line is the Z_TARGET and the dotted vertical brown line is the f_TARGET. The solid red Z_EFF line has been designed by using various decoupling and bulk capacitors such that its impedance remains below the Z_TARGET from DC up to f_TARGET. With this design, power integrity is achieved from DC up to the target frequency of decoupling.

To design a reliable decoupling scheme using the FDTIM, perform the following calculations:

Determine Z_TARGET

To calculate Z_TARGET for a power rail, you must know the following information:

• Maximum transient current requirements for all devices in the system that are powered by the power rail under consideration. You can get this information the from manufacturers of the respective devices. Note: Altera provides the PowerPlay Early Power Estimator (EPE) tool to estimate power consumption for all its FPGAs and CPLDs.
• Maximum allowable AC ripple on the power rail as a percentage of the supply voltage. You can get this information from the power supply tolerance specifications of the devices being supplied by the power rail under consideration.

If this information is available, then Z_TARGET can be calculated as:

• Z_TARGET= [VoltageRail (%Ripple/100)/MaxTransientCurrent]

For example, to reliably decouple a 1.1-volt power rail that allows 5 percent of AC ripple and is expected to supply a maximum transient current of 1.5 A, the target impedance is:

• Z_TARGET= [(1.1)(0.05)/1.5]=36.7mΩ

Determine f_TARGET

The highest frequency of interest is the point in frequency after which adding a reasonable number of decoupling capacitors does not bring down the power rail impedance (Z_EFF) below the target impedance (Z_TARGET) due to the dominance of the parasitic planar spreading inductance and package mounting inductances. Typically, this f_TARGET ranges from 50/60 MHz to 150/200 MHz. Beyond these frequencies, it is expected that power integrity is maintained and performed by the on-package and on-die capacitors of the selected target devices.

Select Decoupling CAPS to Meet Z_TARGET

To maintain power integrity throughout the entire frequency range of interest, the Power Distribution System relies on the voltage regulator module (VRM), the on-board discrete decoupling capacitors, and inter-plane capacitances (capacitance from the power-ground sandwich in the board stack-up). For the above example, the designer must select these appropriately so that the effective impedance remains below 36.7 Ω within the entire frequency range of interest.

For more details on applying the FDTIM, refer to the Altera PDN Decoupling Calculator Tool and its corresponding User Guide.

• Voltage Regulator Selection for FPGAs white paper (PDF)

• Power Delivery Network (PDN) Tool User Guide (PDF)
  • Power Delivery Network (PDN) Tool (ZIP)
• Device-Specific Power Delivery Network (PDN) Tool User Guide for Stratix V, Arria V, Arria II GZ, Cyclone V, and Cyclone IV Device Families (PDF)
  • Power Delivery Network (PDN) Tool for Arria^® V, Stratix^® V, Cyclone^® IV,  and Arria II GZ Devices (ZIP) 
• Device-Specific Power Delivery Network (PDN) Tool User Guide (PDF)
  • Power Delivery Network (PDN) Tool for Arria II GX Devices
  • Power Deliver Network (PDN) Tool for Stratix IV Devices
  • Power Deliver Network (PDN) Tool for Stratix III Devices

For high frequencies, decoupling using discrete capacitors is less effective. Use power plane capacitance for decoupling noise at these frequencies. You can understand the concept of plane capacitance by studying the classic parallel plate capacitor, shown in Figure 1.

Figure 1. Parallel Plane Capacitance

An electric field is created when there is a power plane next to a ground plane. The upper area in Figure 1 shows the power island or plane, the lower area shows the ground plane, and the arrows represent the electric field lines. This electric field gives rise to a capacitance, the magnitude of which is shown by the following equation:

• C=(ε_οε_rA)/h

Where

• ε_ο = permittivity of free space
• ε_r = relative permittivity of the dielectric used
• A = area of overlap
• h = separation of the planes.

  If there are ground planes on both sides of the power island, then the capacitance needs to be calculated for each side and added to determine the total capacitance.

  Plane capacitance is the primary way of decoupling at high frequencies, so it must be an integral part of any high-speed design. At high frequencies, the discrete capacitors are not very effective.

  As an example, consider the following.

  Example: Determine the parallel plate capacitance for 1 square inch of area overlap in an FR-4 dielectric (ε_r = 4.5) and a separation of 4 mils.

  Solution:

  • h = 4mils = 1.016 * 10-4 m
  • ε_ο = permittivity of free space = 8.85 * 10^-12 F/m
  • A = 1 sq inch = 6.4516 * 10^-4 m2
  • ε_r = 4.5

  Applying these numbers to the capacitance equation above yields C = 253 pF.  Therefore, there is about 253 pF per square inch of area overlap on a typical FR-4 board with 4 mils of separation.  The value scales inverse linearly with separation and linearly with area.  Altera has successfully used plane capacitance in several of its boards.

The goal of a Power Distribution System (PDS) is to provide and maintain a target constant voltage at the power and ground pads of each device. To effectively accomplish this, the PDS relies on the Voltage Regulator Module (VRM), the bulk and decoupling capacitors (Decaps) and the power and ground plane sandwich (plane capacitance). How effectively each of these components perform their job in helping to maintain a constant voltage under varying transient loads depends highly on their associated parasitic inductances.

VRM

As a first-order approximation, the VRM can simply be modeled as a series connected resistor and inductor, as shown in Figure 1.

Figure 1. Series Impedance Model of a VRM

At low frequencies in the range of tens of KHz, the VRM, being primarily resistive, provides very low impedance and thus it is capable of providing the instantaneous current requirements at these lower frequencies. However, beyond a few tens of KHz, the VRM impedance being primarily inductive makes it incapable of providing the transient current requirements. You can get the ESR and ESL values of the VRM from the VRM manufacturer and you can choose a low ESR/ESL regulator for best transient performance.

Decaps

The on-board discrete decoupling capacitors must provide the required low impedance from a few tens of KHz to about a couple of hundred MHz (maximum) depending upon the capacitor ESR and ESL as well as board mounting and spreading inductance parasitics. Even choosing decoupling capacitors with very low ESR and ESL specifications is not enough as the contribution of the parasitic mounting and spreading inductances can limit the effectiveness of these capacitors. Hence, to design an effective PDS, care must be taken to minimize the various parasitic inductances associated with the design of the board.

Mounting Inductance

Mounting Inductance is the additional series inductance contribution associated with the mounting of the capacitor on the PCB. This parasitic inductance adds to the published ESL value that is provided by the cap vendor. Mounting inductance can be minimized by choosing smaller capacitor packages and performing proper layout of the capacitor on the PCB. Figure 2 shows the cross-section of a mounted decoupling capacitor in relation to the PCB planes and BGA device.

Figure 2. Decoupling Cap Mounting

To estimate the mounting inductance, use the following equation:

• Lmnt = Ltrace + Lvia

Where,

• Ltrace = 128*[(2xLen_pad)+Len_cap]*(htop/w) pH

And,

• Lvia = 10*htop*ln(2s/D) ph

Where,

• Len_pad = Length of the capacitor pads plus trace length from pad to the via (mils)
• Len_cap = Length of the capacitor body (mils)
  
• w = Width of the trace between the capacitor pad and via (mils)
• htop = Distance between the top layer and the nearest power/ground plane (mils)
• s = Distance between the capacitor's power via center and ground via center (mils)
• D = Outer diameter of the via (mils)
• hplanes = Distance between the power and ground plane (mils)
• b = Half the distance between the capacitor and the package power/ground vias (mils)

Generally, to minimize the mounting inductance, keep the capacitors power and ground vias as close as possible to its respective pad and use wide connecting traces and larger via drill diameters, if possible. Placing power and ground plane pairs closer to the surface where the capacitor is mounted reduces the via inductance contribution. Additionally, placing the vias on the same sides of the capacitor (via-on-side configuration) as opposed to the opposite ends of the capacitor (via-on-end configuration) reduces the current loop area, minimizing the amount of flux lines that penetrate the loop and thus reduces the inductance. Figure 3 illustrates the various capacitor layout topologies while Table 1 compares mounting inductances of those various cap layout styles for different size capacitors.

Figure 3. Various Capacitor Layout Topologies

Note:

• All Values are in nano-Henries and drill sizes are in inches

As shown in Table 1, the optimum mounting inductance of 0.50 nH is obtained when the smaller 0402 size capacitor is mounted using the via-on-side scheme with wide connecting traces to the larger 20 mil via drill diameter. Figure 4 shows other recommended via placement configurations that further reduce mounting inductance. However, these styles require additional vias and hampers routability.

Figure 4. Via placement Styles that Yield Lower Mounting Inductance

Spreading Inductance

Spreading Inductance is the inductance formed by the loop area between the power-ground plane pair and the distance from the decoupling cap to the power-ground balls of the target BGA device. As a result, this inductance is directly related to the inductance of the inter-plane capacitance formed by the power-ground sandwich. This inductance is explained in detail in the inter-plane capacitance section below.

Inter-Plane Capacitance

As a first-order analysis, the PCB power-ground plane pair can simply be modeled as a series connected resistor, inductor, and, capacitor as shown in Figure 5. Note that this simple model ignores the frequency dependent effects such as skin effect and dielectric absorption.

Figure 5. Simplified Impedance Model of the Power-Ground Plane Sandwich

The first-order equations for the ESL in Figure 5 is shown below:

• ESL = (μ0•h•l)/w

Where,

• μ0 = magnetic permeability of free space (32 pH/mil)
• h = distance between the power and ground planes in mils
• l = length of the power plane in inches
• w = width of the power plane in inches

You can interpret the ESL of the power-ground plane sandwich as the spreading inductance that the decoupling capacitor sees as it is supplying current to the BGA device. Therefore, from the ESL equation above, the spreading inductance can be reduced by placing the decoupling capacitors as close as possible to the target BGA device (minimizing the distance l from the cap to the BGA device). Additionally, using a thin dielectric material (minimizing h) and wide plane pairs (maximize w) for the power-ground plane sandwich helps reduce the effective spreading inductance seen by the decoupling capacitor.

Conclusion

To successfully design an effective PDS requires an understanding of the various parasitic inductances that can limit the performance of the PDS. This document explains three parasitic inductances that you must be concerned with in designing the PDS. VRM parasitic inductance, decoupling capacitor mounting inductance, and power plane spreading inductance are examined and techniques to minimize them are presented. For additional information and tools, Altera also provides a PDN Decoupling Calculator tool and user guide available on www.altera.com.

• High-Speed Board Design Advisor: Power Distribution Network (PDF)
• Learn Power Delivery Network (PDN) Best Design Practices for High-Speed Boards webcast
• Stratix III FPGA Signal Integrity white paper (PDN section) (PDF)
• Power Distribution Network Design for Stratix III and Stratix IV FPGAs (OPDN1100) 0.5 Hours Online Course

• AN 528: PCB Dielectric Material Selection and Fiber Weave Effect on High-Speed Channel Routing (PDF)

• Gigabit Channel Design Guidelines webcast

• AN 529: Via Optimization Techniques for High-Speed Channel Designs (PDF)

• AN 528: PCB Dielectric Material Selection and Fiber Weave Effect on High-Speed Channel Routing (PDF)

• AN 530: Optimizing Impedance Discontinuity Caused by Surface Mount Pads for High-Speed Channel Designs (PDF)

Typical transmission media like copper trace and coaxial cable have low pass characteristics, so they attenuate higher frequencies more than lower frequencies. A typical digital signal that approximates a square wave contains high frequencies near the switching region and low frequencies in the constant region. When this signal travels through low pass media, its higher frequencies are attenuated more than the lower frequencies, resulting in increased signal rise times. Consequently, the eye opening narrows and the probability of error increases.

The high-frequency content of a signal is also degraded by what is called "skin effect." The cause of skin effect is the high-frequency current that flows primarily on the surface (skin) of a conductor. The changing current distribution causes the resistance to increase as a function of frequency.

You can use pre-emphasis to compensate for the skin effect. By Fourier analysis, a square wave signal contains an infinite number of frequencies. The high frequencies are located in the low-to-high and high-to-low transition regions and the low frequencies are located in the flat (constant) regions. Increasing the signal's amplitude near the transition region emphasizes higher frequencies more than the lower frequencies. When this pre-emphasized signal passes through low pass media, it will come out with minimal distortion, if you apply the correct amount of pre-emphasis. See Figure 1 for a graphical illustration of this concept.

Figure 1. Input and Output Signals with and without Pre-Emphasis

Stratix II GX and Stratix IV GX devices provide programmable pre-emphasis to compensate for variable lengths of transmission media. You can set the pre-emphasis to be between 5 percent and 25 percent, depending on the value of the output differential voltage (VOD). Please refer to the Stratix II GX and Stratix IV GX user guides.

Related Links

• PELE Technology
• Differences Between the Stratix GX & Stratix II GX Transceivers
• Stratix II GX Transceiver FPGAs Physical Medium Attachment Layer
• Using Pre-Emphasis and Equalization with Stratix GX white paper (PDF)

• Gigabit Channel Design Guidelines webcast
• High-Speed Board Design Advisor: High-Speed Channel Design and Layout technical brief (PDF)
• PELE Technology

• AN 528: PCB Dielectric Material Selection and Fiber Weave Effect on High-Speed Channel Routing (PDF)

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• On-Chip Debugging Resource Center

• On-Chip Hot-Socketing & Power-Sequencing Support in Altera Devices
• Altera Hot-Socketing & Power-Sequencing Advantages white paper (PDF)
• Hot Socketing and Power-On Reset in Stratix III Devices (PDF), Chapter 10 of the Stratix III Handbook
• Hot Socketing & Power-On Reset (PDF), Chapter 4 of the Stratix II Handbook
• Hot Socketing and Power-On Reset in Cyclone III Devices (PDF), Chapter 11 of the Cyclone III Handbook
• Hot Socketing & Power-On Reset (PDF), Chapter 4 of the Cyclone II Handbook
• Hot Socketing and Power-On Reset in MAX II Devices (PDF), Chapter 4 of the MAX II Handbook

• AN 465: Implementing OCT Calibration in Stratix III Devices (PDF)
• AN 384: Using Calibrated On-Chip Series Termination in Stratix II Devices (PDF)

To allow flexibility in board design, you can specify the state of unused pins as one of the following five states in the Quartus^® II software: as inputs that are tri-stated, as outputs that drive ground, as outputs that drive an unspecified signal, as input tri-stated with bus-hold, or as input tri-stated with weak pull-up resistors. To improve signal integrity, set unused pins as outputs that drive ground and tie them directly to the ground plane on the board. Doing so reduces inductance by creating a shorter return path and reduces noise on the neighboring I/O. To reduce power dissipation, set clock pins to drive ground and set other unused I/O pins as inputs that are tri-stated. To make the setting that is appropriate for your design, choose one of the five allowable states for Reserve all unused pins on theUnused Pins tab in the Device & Pin Options dialog box, or apply the Reserve Pin assignment to specific pins in the Pin Planner.

When you compile your design, the Quartus II software generates the pin report file (.pin) to specify how you should connect the device pins. Unused I/O pins are marked in the report file according to the unused pins option you set in the Quartus II software. All I/O pins specified as GND* can either be connected to ground to improve the device's immunity to noise, or left unconnected. Leave all RESERVED I/O pins unconnected on your board because these I/O pins drive out unspecified signals. Tying a RESERVED I/O pin to V_CC, ground, or another signal source can create contention that can damage the device output driver. You can connect RESERVED_INPUT I/O pins to a high or low signal on the board, while RESERVED_INPUT_WITH_WEAK_PULLUP and RESERVED_INPUT_WITH_BUS_HOLD pins can be left unconnected.

• FineLine BGA Gerber Files & Layout Guidelines

• High-Speed Board Design Advisor: Pinout Definition technical brief (PDF)

A typical high-speed board design begins with a product requirements document, a concept review, and a functional specification. After the specification is finalized, actual system design begins with the selection of key components. At this point, timing analysis for all the interfaces and power analysis — to determine the power requirements — is performed. Based on the power analysis, power supply modules and regulators are chosen, and a decoupling scheme is specified. Based on the timing analysis, a length-matching criterion for the buses is established. Upon completion of these tasks, as well as completion of the system design and selection of remaining components, the schematics are created. These are typically reviewed among engineers who make any necessary changes, after which they are given to the layout designer. A layout guidelines document, which specifies how to place components on the board and how to route the traces, is created and given to the layout designer as well.

A pre-layout simulation is performed to determine the ideal stack-up, trace widths, spacing, and other routing requirements. Any changes to the schematic, based on the simulation results, are incorporated in the schematic and provided to the layout designer. When the layout is complete, a post-layout simulation is performed on the critical sections of the board to ensure that there are no major signal integrity problems.

Based on the results of the post-layout simulation, any changes required are incorporated into the layout, and finally the layout is released to the fabrication house for board manufacturing. Figure 1 shows typical board design process.

Figure 1. Simplified View of a Typical High-Speed Board Design Process

• AN 528: PCB Dielectric Material Selection and Fiber Weave Effect on High-Speed Channel Routing (PDF)

Crosstalk is the unwanted coupling of signals between parallel traces. Proper routing and layer stack-up through microstrip and stripline layouts can minimize crosstalk.

To reduce crosstalk in dual-stripline layouts, which have two signal layers next to each other (see Figure 1), route all traces perpendicular, increase the distance between the two signal layers, and minimize the distance between the signal layer and the adjacent reference plane.

Figure 1.  Dual-Stripline Layout

Use the following steps to reduce crosstalk in either microstrip or stripline layouts:

• Widen spacing between signal lines as much as routing restrictions will allow. Try not to bring traces closer than three times the dielectric height.
• Design the transmission line so that the conductor is as close to the ground plane as possible. This technique will couple the transmission line tightly to the ground plane and help decouple it from adjacent signals.
• Use differential routing techniques where possible, especially for critical nets (i.e., match the lengths as well as the gyrations that each trace goes through).
• If there is significant coupling, route single-ended signals on different layers orthogonal to each other.
• Minimize parallel run lengths between single-ended signals. Route with short parallel sections and minimize long, coupled sections between nets.

Crosstalk also increases when two or more single-ended traces run parallel and are not spaced far enough apart. The distance between the centers of two adjacent traces should be at least four times the trace width, as shown in Figure 2. To improve design performance, lower the distance between the trace and the ground plane to under 10 mils without changing the separation between two traces.

Figure 2.  Separating Traces for Crosstalk

Clean, evenly distributed power to V_CC on all boards and devices can reduce system noise.

Filtering Noise

To diminish the low-frequency (< 1 kHz) noise caused by the power supply, filter the noise on the power lines at the point where the power connects to the PCB and to each device. You may place a 100-μF electrolytic capacitor adjacent to the location where the power supply lines enter the PCB. If using a voltage regulator, place the capacitor immediately after the final stage that provides the V_CC signal to the device(s). Capacitors not only filter low-frequency noise from the power supply, but also supply extra current when many outputs switch simultaneously in a circuit.

Another way to filter power supply noise is to place a non-resonant surface-mount ferrite bead, big enough to handle the current, in series with power supply. Place a 10-μF to 100μF bypass capacitor next to the ferrite bead (see Figure 1). Proper terminations, layouts, and filtering in a design eliminate the need for the ferrite bead. In this case, use a 0-Ω resistor instead of the ferrite bead.

Figure 1.  Filtering Noise with Ferrite Bead

PCB elements add high-frequency noise to the power plane. To filter high-frequency noise at the device, Altera recommends placing decoupling capacitors as close as possible to each V_CC and ground pair. Placing the power and ground planes in parallel and separated by dielectric material provides another level of bypass capacitance. These parallel planes reduce the power-related high-frequency noise, since this type of capacitance has no effective series resistance (ESR) and no lead inductance.

Distributing Power

Power distribution also impacts system noise. Either a power bus network or power planes can distribute power throughout the PCB. Usually used on two-layer PCBs, the least expensive way to distribute power is a power bus network, which consists of two or more wide metal traces that carry V_CC and ground to the devices. The density of the PCB limits the trace widths, which should be as wide as possible. Power buses have significant DC resistance; the last element on the bus may receive V_CC power degraded by as much as 0.5 V.

Altera recommends using power planes to distribute power. Used on multi-layer PCBs, power planes consist of two or more metal layers that carry V_CC and ground to the devices. Because the power plane covers the full area of the PCB, its DC resistance is very low. The power plane maintains V_CC, distributes it equally to all devices, and provides very high current-sink capability, noise protection, and shielding for the logic signals on the PCB. Sharing the same plane between analog and digital power supplies may be risky due to unwanted interaction of these two circuit types.

For fully digital systems without separate analog power and ground planes on the board, adding two new planes to the board may be prohibitively expensive. Instead, you can create partitioned power islands (split plane). Figure 2 shows an example board layout with phase-locked loop (PLL) power islands.

Figure 2. Board Layout for General-Purpose PLL Power Islands

To reduce system noise from power distribution:

• Use separate power planes for the analog power supply for equal power distribution.
• Avoid trace and multiple signal layers when routing the PLL power supply.
• Place a ground plane next to the PLL power supply plane. Place analog and digital components only over their respective ground plane.
• Use ferrite beads to isolate the PLL power supply from the digital power supply.

To allow flexibility in board design, you can specify the state of unused pins as one of the following five states in the Quartus^® II software: as inputs that are tri-stated, as outputs that drive ground, as outputs that drive an unspecified signal, as input tri-stated with bus-hold, or as input tri-stated with weak pull-up resistors. To improve signal integrity, set unused pins as outputs that drive ground and tie them directly to the ground plane on the board. Doing so reduces inductance by creating a shorter return path and reduces noise on the neighboring I/O. To reduce power dissipation, set clock pins to drive ground and set other unused I/O pins as inputs that are tri-stated. To make the setting that is appropriate for your design, choose one of the five allowable states for Reserve all unused pins on theUnused Pins tab in the Device & Pin Options dialog box, or apply the Reserve Pin assignment to specific pins in the Pin Planner.

When you compile your design, the Quartus II software generates the pin report file (.pin) to specify how you should connect the device pins. Unused I/O pins are marked in the report file according to the unused pins option you set in the Quartus II software. All I/O pins specified as GND* can either be connected to ground to improve the device's immunity to noise, or left unconnected. Leave all RESERVED I/O pins unconnected on your board because these I/O pins drive out unspecified signals. Tying a RESERVED I/O pin to V_CC, ground, or another signal source can create contention that can damage the device output driver. You can connect RESERVED_INPUT I/O pins to a high or low signal on the board, while RESERVED_INPUT_WITH_WEAK_PULLUP and RESERVED_INPUT_WITH_BUS_HOLD pins can be left unconnected.

Proper routing helps to maintain signal integrity. To route a clean trace, you should perform simulation with good signal integrity (SI) tools. The following section describes the two different types of signal traces available for routing:

• Single-ended trace
• Differential pair trace

To minimize skew, make sure the two traces of a differential pair are equal lengths. If there is skew between pair traces and if the traces are loosely coupled, the traces can be designed as shown in Figure 1.To control the trace length, the traces separate and come back together. Because the traces are loosely coupled, the impedance is just slightly affected.

Figure 1. 45° Turns on the Serpentine Traces

When using serpentine traces, you should have 45° bends (see Figure 1). Figure 2 shows another example using serpentine traces. However, when using the design shown in Figure 2, make sure there is no coupling between the adjacent lines. When using serpentine traces for high-speed applications, you should avoid having the traces run parallel to each other at any point. See the example shown in Figure 1.

Figure 2. Example of Serpentine Traces

Figure 3 shows skew control for tightly coupled pairs. Because the traces are tightly coupled, the impedance changes when the traces are separated and then brought closer together. In a tightly coupled pair, skew-matching is performed at the pin level.

Figure 3. Skew Control Tightly-Coupled Differential Pairs

When designing traces on adjacent signal layers, the traces should not cross each other unless they are almost perpendicular. Parallel traces on adjacent signal layers will have coupling between the traces.

Mismatched impedance causes signals to reflect back and forth along the lines, which causes ringing at the load receiver. The ringing reduces the dynamic range of the receiver and can cause false triggering. To eliminate reflections, the impedance of the source (Z_S) must equal the impedance of the trace (Z₀), as well as the impedance of the load (Z_L). Stratix devices feature support for on-chip implementation of a termination resistor. This section discusses the following signal termination schemes:

• Simple parallel termination
• Thevenin parallel termination
• Active parallel termination
• Series-RC parallel termination
• Series termination
• Differential pair termination
• On-chip termination

As digital devices become faster, their output switching times decrease. Faster switching times cause higher transient currents in outputs as they discharge load capacitances. These higher currents, which are generated when multiple outputs of a device switch simultaneously from a logic high to a logic low, can cause a board-level phenomenon known as ground bounce.

Many factors contribute to ground bounce. Therefore, no standard test method predicts ground bounce magnitude for all possible PCB environments. Determine each condition's and each device's relative contributions to ground bounce by testing the device under these conditions: Load capacitance, socket inductance, and the number of switching outputs, which are the predominant conditions that influence the magnitude of ground bounce in programmable logic devices (PLDs).

Design Guidelines

Altera recommends the following design methods to reduce ground bounce:

• Add decoupling capacitors for as many V_CC/GND pairs as possible.
• Place the decoupling capacitors as close as possible to the power and ground pins of the device.
• Add external buffers at the output of a counter to minimize the loading on Altera^® device pins.
• Configure the unused I/O pin as an output pin and then drive the output low. This configuration acts as a virtual ground. Connect this low driving output pin to GNDINT and/or the board's ground plane.
• Any unused I/O pin may be driven to ground by programming the “programmable ground” bit (one per I/O cell). In doing so, the macrocell does not need to be sacrificed, but can be used as a buried macrocell.
• When speed is not critical, turn on the slow slew rate logic option.
• Limit load capacitance by buffering loads with an external device, or by reducing the number of devices that drive the bus.
• Eliminate sockets whenever possible.
• Reduce the number of outputs that can switch simultaneously and/or distribute them evenly throughout the device.
• Move switching outputs close to a package ground pin.
• Create a programmable ground next to switching pins.
• Eliminate pull-up resistors or use pull-down resistors.
• Use multi-layer PCBs that provide separate V_CC and ground planes.
• Add appropriate resistors in series to each of the switching outputs to limit the current flow into each of the outputs.
• Create synchronous designs that are not affected by momentarily switching pins.
• Assign I/O pins to minimize local bunching of output pins.
• Place the power and ground pins next to each other. The total inductance is reduced by mutual inductance, because current flows in opposite directions in power and ground pins.
• Use a bigger via size to connect the capacitor pad to the power and ground plane to minimize the inductance in decoupling capacitors.
• Use the wide and short trace between the via and the capacitor pad or place the via adjacent to the capacitor pad. See Figure 1.

Figure 1. Suggested Via Location that Connects to Capacitor Pad

• Use surface mount capacitors to minimize the lead inductance.
• Use low effective series resistance (ESR) capacitors. The ESR should be < 400 mΩ.
• Each GND pin/via should be connected to the ground plane individually.
• To add extra capacitance on the board, Altera recommends placing a ground plane next to each power (V_CC) plane. This placement gives zero lead inductance and no ESR. The dielectric thickness between the two planes should be ~5 mils.

These design guidelines provide information and help for high-speed logic designs operating over a range of PCB conditions.

The transmission line is a trace and has a distributed mixture of resistance (R), inductance (L), and capacitance (C). There are two types of transmission line layouts:

• Microstrip
• Stripline

Figure 1 shows a microstrip layout, which refers to a trace routed as the top or bottom layer of a PCB and has only one voltage-reference plane (i.e., power or GND). Figure 2 shows a stripline layout, which uses a trace routed on the inside layer of a PCB and has two voltage-reference planes (i.e., power and/or GND).

Figure 1. Microstrip Transmission Line Layout

Figure 2. Stripline Transmission Line Layout

Notes to Figures 1 and 2:

• W = width of trace, T = thickness of trace, and H = height between trace and reference plane.
• W = width of trace, T = thickness of trace, and H = height between trace and two reference planes.

There are three types of coplanar wave guides: simple, grounded, and grounded differential.

Simultaneous switching noise (SSN) is another important factor to consider when designing a PCB. Although SSN is dominant on the device package, the board layout can help reduce some of the noise.

Every current loop has an inductance value. The current loop in Figure 1 has the following inductance:

• L_loop = L₁ (signal) + L₂ (GND) – 2 L_M (mutual inductance)

Figure 1. Inductance Due to a Current Loop

When a driver switches from high to low, a voltage develops in the GND plane, thus:

• V = L_loop (di/dt)

The noise that develops in the GND plane can become a problem for signal-integrity, especially when there are a lot of drivers switching simultaneously. The noise generated by SSNs can couple to adjacent structures. Proper layout and decoupling reduces noise coupling. The high number of simultaneously switching drivers can cause the power supply to collapse. Thus, the power supply voltage at a certain region loses some of its strength, depending on where the switching is concentrated.

For more information, refer to the following:

• AN 472: Stratix II GX SSN Design Guidelines (PDF)
• AN 508: Cyclone III Simultaneous Switching Noise (SSN) Design Guidelines (PDF)

Please refer to the following documents:

• Design Security in Stratix III Devices (PDF) chapter of the Stratix III Device Handbook
• AN 341: Using the Design Security Feature in Stratix II and Stratix II GX Devices (PDF)

Electromagnetic interference (EMI) is directly proportional to the change in current or voltage with respect to time. EMI is also directly proportional to the series inductance of the circuit. Every PCB generates EMI.

Precautions such as minimizing crosstalk, proper grounding, and proper layer stack-up can significantly reduce EMI problems.

Place each signal layer in between the ground plane and power plane. Inductance is directly proportional to the distance an electric charge has to cover from the source of an electric charge to ground. As the distance gets shorter, the inductance becomes smaller as well. Therefore, placing ground planes close to a signal source reduces inductance and helps contain EMI. Figure 1 shows an example of an eight-layer stack-up. In the stack-up, the stripline signal layers are the quietest because they are centered by power and GND planes. A solid ground plane next to the power plane creates distribution capacitances with low equivalent series inductance (ESL). With IC edge rates becoming faster, these techniques help to contain EMI.

Figure 1. Example Eight-Layer Stack-Up

Component selection and proper placement on the board is very important to controlling EMI. The following guidelines can help reduce EMI:

• Select low-inductance components, such as surface mount capacitors with low ESR and ESL
• Provide good return path to minimize lop inductance
• Use solid ground planes next to power planes
• Use adjacent ground planes next to each segmented power plane for analog and digital circuits

Deciding which components to use is an important part of board design. Information and guidelines for selecting discrete components for the PCB is provided below.

It is difficult to define voltages or currents in transmission lines and to measure them at microwave frequencies, because direct measurements usually involve the magnitude (inferred from power) and phase of a wave traveling in a given direction or the standing wave. Thus, equivalent voltages and currents, and the related impedance and admittance matrices, become somewhat of an abstraction when dealing with high-frequency networks.

A representation more consistent with direct measurements, and with the ideas of incident, reflected, and transmitted waves, is provided by the scattering matrix (S-parameters). S-parameters are often used to quantify the impedance, total losses, input return loss, insertion loss, and isolation and crosstalk for the different transmission lines structures. These concepts are most useful at those frequencies where you must consider distributed rather than lumped parameters.

To understand S-parameters, consider the two-port network shown in Figure 1. The network can contain a transmission line or any linear time invariant component. The incident voltages at ports 1 and 2 are E₁₁ and E₁₂; and the reflected voltages are E_R1 and E_R2. Z₀ is the characteristic impedance of the transmission line. Z_S and Z_L are the source and the load impedances.

Figure 1. S-Parameters

Taking the incident and reflected voltage waves on each side of the two port network and dividing them by the square root of the characteristic impedance, Z₀, results in new variables (a₁, a₂, b₁, and b₂), which are the normalized voltage wave amplitudes at each port.

The square of the magnitude of a₁ (| a₁|²) represents the incident power in port 1, and (| b₁|²) represents the reflected power from this port. The same relations apply to port 2.

• a₁=E_I1/√Z₀ a₂=E_I2/√Z₀
• b₁=E_R1/√Z₀ b₂=E_I2/√Z₀

The resulting parameters relate the scattered wave (reflected wave) from the network to the incidents waves. These parameters are called S-parameters and are defined by:

• b₁=S₁₁a₁+S₁₂a₂
• b₂=S₂₁a₁+S₂₂a₂

Where, S₁₁ is the input reflection coefficient, S₂₁ is the forward transmission through the network, S₁₂ is the reverse transmission through the network, and S₂₂ is the output reflection coefficient.

The measurement setup for S-parameters is shown in Figure 2 and Figure 3. Apply the following conditions for these measurements:

• S₁₁=(a₁/b₁) | a₂=0
• S₂₁=(b₂/a₁) | a₂=0
• S₁₂=(b₁/a₂) | a₁=0
• S₂₂=(b₂/a₂) | a₁=0

Figure 2. Measurement Setup for S₁₁ and S₂₁

Figure 3. Measurement Setup for S₂₂ and S₁₂

For example, to measure S₁₁, ensure that a₂ = 0. Do this by making sure that there is no reflection from the load (in other words, set Z_L = Z₀).

S-parameters are typically measured using network analyzers.

The Smith Chart is a graphical representation of the impedances in a complex plane. You can use this to analyze transmission line impedance matching networks and capacitive or inductive behavior of loads. Figure 1 shows a typical Smith Chart. If the impedance is inductive, it shows up in the top half of the circle; if it is capacitive, it shows up in the bottom half. The far-right point in the middle represents an open circuit; the far left represents a short circuit. The middle point (label 1.0) represents a perfect load match to the characteristic impedance of the line.

Figure 1. Smith Chart

AC coupling refers to the use of a series capacitor on a signal to block the DC signals from going through. DC coupling refers to the case where this capacitor is not present and the signal passes through without any interruption. In AC coupling, a DC restore circuit is generally required after the capacitor to ensure that the common mode voltage requirements of the receiver are met. In Altera^® devices with transceivers, the DC restore circuitry is built into the device. In that case, external DC restore circuitry is not necessary. DC coupling works only in cases where the output common mode voltage of the transmitter is in the required range of the input common mode voltage of the receiver.

The advantage of AC coupling is that it allows chips with different common mode voltages to interface with each other. The disadvantage is that it requires an extra capacitor, which can add some jitter or other degradation if not properly selected.

If you are certain that the common mode voltage requirements of the receiver are a subset of the common mode voltage output of the transmitter, use DC coupling. If you are in a borderline case, or if the requirements are not satisfied, then use AC coupling.

In choosing the value of the coupling capacitor, consider what happens if the capacitor is too big or too small. If the capacitor is too big, it can significantly slow the signal down and can also respond poorly to fast changing input signals because of the long charge and discharge times. If the capacitor is too small, it presents a fair amount of impedance and can increase attenuation and change the characteristic impedance of the path. A good balance between these two conflicting requirements is a 0.01 μF capacitor, which Altera uses for its 3.125 Gbps transceiver designs.

When selecting components, use the smallest size possible, because smaller size components have smaller size pads, which reduce the discontinuity. Altera has used 0402 components (40 mils x 20 mils) in its designs.

You can design the DC restore circuitry in a variety of ways. Altera typically uses a simple resistive voltage divider (see Figure 1). Be sure to use precision resistors (0.1% or 1%) for differential signals, so that the restored DC levels on the positive and negative signals are very closely matched. In Figure 1, the DC restore circuitry restores the DC level to 3.3 * 78.7/(140 + 78.7) = 1.1875 volts.

Figure 1. AC Coupling

Transceiver devices have DC biasing on the high-speed transceivers inputs and reference clock inputs designed for the 1.5-V PCML standard, so AC coupling is not required. This saves components and board space. If you are using other I/O standards such as LVPECL or LVDS, then you need to AC-couple them, because their common mode voltage is different from the 1.5-V PCML common mode voltage. External biasing networks are not needed, because the common mode is generated internally in the device.

• Stratix III Signal Integrity white paper (PDN section) (PDF)
• FPGA Design for Signal and Power Integrity (DesignCon paper)
• Signal & Power Integrity Design Techniques for SSN webcast

• AN 436: Design Guidelines for Implementing DDR3 SDRAM Interfaces in Stratix III Devices (PDF)
• AN 520: DDR3 SDRAM Memory Interface Termination and Layout Guidelines (PDF)

• AN 328: Interfacing DDR2 SDRAM with Stratix II, Stratix II GX, and Arria GX Devices (PDF)
• AN 408: DDR2 Memory Interface Termination, Drive Strength, Loading, and Design Layout Guidelines (PDF)
• AN 444: Dual DIMM DDR2 SDRAM Memory Interface Design Guidelines (PDF)
• AN 445: Design Guidelines for Implementing DDR and DDR2 SDRAM Interfaces in Cyclone III Devices (PDF)
• AN 361: Interfacing DDR & DDR2 SDRAM with Cyclone II Devices (PDF)

• AN 445: Design Guidelines for Implementing DDR and DDR2 SDRAM Interfaces in Cyclone III Devices (PDF)
• AN 361: Interfacing DDR & DDR2 SDRAM with Cyclone II Devices (PDF)
• AN 348: Interfacing DDR SDRAM with Cyclone Devices (PDF)
• AN 342: Interfacing DDR SDRAM with Stratix and Stratix GX Devices (PDF)
• AN 336: Using External Series and Parallel Termination with Stratix and Stratix GX Devices (PDF)
• AN 327: Interfacing DDR SDRAM with Stratix II Devices (PDF)

• AN 326: Interfacing QDRII+ & QDRII with Stratix II Stratix II GX, Stratix, & Stratix GX Devices (PDF)

• AN 325: Interfacing RLDRAM II with Stratix II, Stratix, & Stratix GX Devices (PDF)

• Utilizing Leveling Techniques in DDR3 SDRAM Memory Interfaces white paper (PDF)
• Implementing High-Speed DDR3 Interfaces Webcast
• External Memory Solutions Center

• Power Management Resource Center
• AN 448: Stratix III Power Management Design Guide (PDF)

• Thermal Resistance
• AN 358: Thermal Management for FPGAs (PDF)
• AN 185: Thermal Management Using Heat Sinks (PDF) 

• High-Speed Board Design Advisor: Thermal Management technical brief (PDF)
  Stratix III Programmable Power white paper (PDF)

• Early Power Estimator
• PDN Design Tool
  • PDN Design Tool User Guide
• Stratix V Early SSN Estimator and user guide (PDF)
• Stratix II GX Early SSN Estimator and user guide (PDF) 
• Stratix III Early SSN Estimator and user guide (PDF)
• Arria V Early SSN Estimator and user guide (PDF)

• IBIS
• HSPICE

• Orcad Symbols by Device and Package

• Stratix V GX Net Length Information 
• Stratix IV GT Net Length Information 
• Stratix IV GX Net Length Information 
• Stratix IV E Net Length Information 
• Stratix III Net Length Information
• Stratix II GX Net Length Information
• Stratix II Net Length Information
• HardCopy II Net Length Information
• Cyclone III Net Length Information
• Cyclone II Net Length Information
• Arria II GX Net Length Information 
• Arria GX Net Length Information

• Stratix IV GT Flowtherm Models 
• Stratix IV GX Flowtherm Models 
• Stratix IV E Flowtherm Models 
• Stratix III Flotherm Models
• Stratix II Flotherm Models
• Cyclone III Flotherm Models

• Arria^® II GX FPGA Development Kit 
• Audio Video Development Kit, Stratix^® IV GX Edition 
• Cyclone^® III LS FPGA Development Kit 
• DSP Development Kit, Cyclone III Edition 
• DSP Development Kit, Stratix III Edition 
• Embedded Systems Development Kit, Cyclone III Edition 
• Nios^® II Embedded Evaluation Kit, Cyclone III Edition 
• Stratix IV E FPGA Development Kit 
• Stratix IV GX FPGA Development Kit 
• Transceiver Signal Integrity Development Kit, Stratix II GX Edition 
• Transceiver Signal Integrity Development Kit, Stratix IV GX Edition 
• Nios II Development Kit, Stratix
• Nios II Development Kit, Cyclone II Edition
• DSP Development Kit, Stratix II Edition
• DSP Development Kit, Stratix II Professional Edition
• DSP Development Kit, Cyclone II Edition
• Video Development Kit, Cyclone II Edition
• Transceiver Signal Integrity Kit, Stratix II GX Edition
• PCI Express Development Kit, Stratix II GX Edition
• Audio Video Development Kit, Stratix II GX Edition
• PCI Development Kit, Cyclone II Edition
• MAX^® II Development Kit
• Cyclone II FPGA Starter Development Kit
• Cyclone III FPGA Starter Kit
• Cyclone III FPGA Development Kit
• Stratix III FPGA Development Kit